Showing papers by "Chenming Hu published in 1997"

Dynamic threshold-voltage MOSFET (DTMOS) for ultra-low voltage VLSI

Abstract: In this paper, we propose a novel operation of a MOSFET that is suitable for ultra-low voltage (0.6 V and below) VLSI circuits. Experimental demonstration was carried out in a Silicon-On-Insulator (SOI) technology. In this device, the threshold voltage of the device is a function of its gate voltage, i.e., as the gate voltage increases the threshold voltage (V/sub t/) drops resulting in a much higher current drive than standard MOSFET for low-power supply voltages. On the other hand, V/sub t/ is high at V/sub gs/=0, therefore the leakage current is low. We provide extensive experimental results and two-dimensional (2-D) device and mixed-mode simulations to analyze this device and compare its performance with a standard MOSFET. These results verify excellent inverter dc characteristics down to V/sub dd/=0.2 V, and good ring oscillator performance down to 0.3 V for Dynamic Threshold-Voltage MOSFET (DTMOS).

A physical and scalable I-V model in BSIM3v3 for analog/digital circuit simulation

Abstract: A new physical and continuous BSIM (Berkeley Short-Channel IGFET Model) I-V model in BSIM3v3 is presented for circuit simulation. Including the major physical effects in state-of-the art MOS devices, the model describes current characteristics from subthreshold to strong inversion as well as from the linear to the saturation operating regions with a single I-V expression, and guarantees the continuities of I/sub ds/, conductances and their derivatives throughout all V/sub gs/, V/sub ds/, and T/sub bs/, bias conditions. Compared with the previous BSIM models, the improved model continuity enhances the convergence property of the circuit simulators. Furthermore, the model accuracy has also been enhanced by including the dependencies of geometry and bias of parasitic series resistances, narrow width, bulk charge, and DIBL effects. The new model has the extensive built-in dependencies of important dimensional and processing parameters (e.g., channel length, width, gate oxide thickness, junction depth, substrate doping concentration, etc.). It allows users to accurately describe the MOSFET characteristics over a wide range of channel lengths and widths for various technologies, and is attractive for statistical modeling. The model has been implemented in the circuit simulators such as Spectre, Hspice, SmartSpice, Spice3e2, and so on.

Short-channel effect improved by lateral channel-engineering in deep-submicronmeter MOSFET's

Abstract: The normal and reverse short-channel effect of LDD MOSFET's with lateral channel-engineering (pocket or halo implant) has been investigated. An analytical model is developed which can predict V/sub th/ as a function of L/sub eff/, V/sub DS/, V/sub BS/, and pocket parameters down to 0.1-/spl mu/m channel length. The new model shows that the V/sub th/ roll-up component due to pocket implant has an exponential dependence on channel length and is determined roughly by (N/sub p/)/sup 1/4 /L/sub p/. The validity of the model is verified by both experimental data and two-dimensional (2-D) numerical simulation. On the basis of the model, a methodology to optimize the minimum channel length L/sub min/ is presented. The theoretical optimal pocket implant performance is to achieve an L/sub min/ approximately 55/spl sim/60% that of a uniform-channel MOSFET without pocket implant, which is a significant (over one technology generation) improvement. The process design window of pocket implant is analyzed. The design tradeoff between the improvement of short-channel immunity and the other device electrical performance is also discussed.

High-field transport of inversion-layer electrons and holes including velocity overshoot

Abstract: In this paper, we experimentally address the effect of a wide range of parameters on the high-field transport of inversion-layer electrons and holes. The studied parameters include substrate doping level, surface micro-roughness, vertical field strength, nitridation of the gate oxide, and device channel length. We employ special test structures built on Silicon-On-Insulator (SOI) and bulk wafers to accurately measure the high-field drift velocity of inversion-layer carriers. Our findings point to electron velocity overshoot at room temperature, dependence of electron and hole saturation velocities on nitridation of the gate oxide, dependence of the high-field drift velocity on the effective vertical field, and relative insensitivity of electron and hole mobility and saturation velocity to moderate surface roughness.

High-current failure model for VLSI interconnects under short-pulse stress conditions

Abstract: Short-time high joule heating causing thermal breakdown of metal interconnects in ESD/EOS protection circuits and I/O buffers has become a reliability concern. Such failures occur frequently during testing for latchup robustness and during ESD/EOS type events. In this work, heating and failure of passivated TiN/AlCu/TiN integrated circuit interconnects in a quadruple level metallization system of a sub-0.5 /spl mu/m CMOS technology has been characterized under high-current pulse conditions. A model incorporating the heating of the layered metal system and the oxide surrounding it has been developed which relates the maximum allowable current density to the pulse width. The model is shown to be in excellent agreement with experimental results and is applied to generate design guidelines for ESD/EOS and I/O buffer interconnects.

Predicting CMOS speed with gate oxide and voltage scaling and interconnect loading effects

Abstract: Sub-quarter micron MOSFET's and ring oscillators with 2.5-6 nm physical gate oxide thicknesses have been studied at supply voltages of 1.5-3.3 V. I/sub dsat/ can be accurately predicted from a universal mobility model and a current model considering velocity saturation and parasitic series resistance. Gate delay and the optimal gate oxide thickness were modeled and predicted. Optimal gate oxide thicknesses for different interconnect loading are highlighted.

A MOSFET electron mobility model of wide temperature range (77 - 400 K) for IC simulation

Abstract: Based on the physics of scattering mechanisms of MOSFET inversion layer carriers at different temperatures and vertical electric fields, a new unified mobility model of wide temperature (77 - 400 K) and range is proposed for IC simulation. Measurement data taken in a wide range of temperatures and electric fields are compared with the simulation results of a MOSFET current model implementing this new mobility equation. Excellent agreement between the simulation and measurement data is found.

Modelling temperature effects of quarter micrometre MOSFETs in BSIM3v3 for circuit simulation

Abstract: This paper presents the temperature modelling in BSIM3v3 (Berkeley Short-channel IGFET Model version 3), and comparison with measured data for both n- and p-channel devices with a channel length down to a quarter of a micrometre from room temperature up to C. I - V, and are modelled with the temperature dependences of mobility, threshold voltage, saturation velocity and series resistance.

An on-chip, interconnect capacitance characterization method with sub-femto-farad resolution

Abstract: In this paper, a sensitive and simple technique for parasitic interconnect capacitance measurement with 0.01 fF sensitivity is presented. This on-chip technique is based upon an efficient test structure design. No reference capacitor is needed. Only a DC current meter is required for its measurement. We have applied this technique to extract various interconnect geometry capacitances and compared the results to those from 3D simulations.

High-speed resonant-cavity separate absorption and multiplication avalanche photodiodes with 130 GHz gain-bandwidth product

Abstract: Previously it has been shown that resonant-cavity, separate absorption and multiplication (SAM) avalanche photodiodes (APDs) exhibit high peak external quantum efficiency (∼75%), low dark current, low bias voltage (<15 V), and low multiplication noise (0.2

Ion-cut silicon-on-insulator fabrication with plasma immersion ion implantation

Abstract: We report the implementation of ion-cut silicon-on-insulator (SOI) wafer fabrication technique with plasma immersion ion implantation (PIII). The hydrogen implantation rate, which is independent of the wafer size, is considerably higher than that of conventional implantation. The simple PIII reactor setup and its compatibility with cluster-tools offer other ion-cut process optimization opportunities. The feasibility of the PIII ion-cut process is demonstrated by successful fabrication of SOI structures. The hydrogen plasma can be optimized so that only one ion species is dominant. The feasibility of performing ion-cut using helium PIII is also demonstrated.

A simple method for on-chip, sub-femto Farad interconnect capacitance measurement

Abstract: In this letter, a sensitive and simple technique for parasitic interconnect capacitance measurement and extraction is presented. This on-chip technique is based upon an efficient test structure design that utilizes only two transistors in addition to the unknown interconnect capacitance to be characterized. No reference capacitor is needed. The measurement itself is also simple; only a dc current meter is required. Furthermore, the extraction methodology employs a self-checking algorithm to verify that the extracted capacitance value is consistent and accurate. The technique is demonstrated by extracting the capacitance of a single crossover between a Metal 1 line and a Metal 2 of 0.44 fF. The resolution limit is dominated by the matching of the minimum sized transistors used for the test structure. We estimate this resolution limit to be about 0.03 fF.

Accurate determination of ultrathin gate oxide thickness and effective polysilicon doping of CMOS devices

Abstract: We present an efficient and accurate method to characterize the physical thickness of ultrathin gate oxides (down to 25 /spl Aring/) and the effective polysilicon doping of advanced CMOS devices. The method is based on the model for Fowler-Nordheim (F-N) tunneling current across the gate oxide with correction in gate voltage to account for the polysilicon-gate depletion. By fitting the model to measured data, both the gate oxide thickness and the effective poly doping are unambiguously determined. Unlike the traditional capacitance-voltage (C-V) technique that overestimates thin-oxide thickness and requires large area capacitor, this approach results in true physical thickness and the measurement can be performed on a standard sub-half micron transistor. The method is suitable for oxide thickness monitoring in manufacturing environments.

Characterization and modeling of a highly reliable metal-to-metal antifuse for high-performance and high-density field-programmable gate arrays

Abstract: The reliability of a new amorphous silicon/dielectric antifuse is characterized and modeled. Unprogrammed antifuse leakage and time-to-breakdown are functions not only of applied voltage but also of stressing polarity and temperature. Both breakdown and leakage criteria are used to investigate their effects on time-to-fail. A thermal model incorporates the effects of programming and stress currents, ambient temperature, and variation of antifuse resistance with temperature. The measured temperature dependence of antifuse resistance is used for the first time to derive key physical parameters in the model.

Separation by plasma implantation of oxygen (SPIMOX) operational phase space

Abstract: Separation by plasma implantation of oxygen (SPIMOX) has been suggested as an economic alternative for separation by implantation of oxygen (SIMOX) to form the silicon-on-insulator (SOI) structure. The chief advantage of SPIMOX is the high throughput and low-cost implanter. The operation regime of implantation for SPIMOX, which uses dc plasma immersion ion implantation (PIII) for the oxygen implantation, has been studied in the phase space of implantation time and chamber pressure during implantation. The phase space is developed for a definite implantation voltage and dose which are dependent on the dimensions of the SOI structure to be fabricated. The effects of dose, implantation voltage, and fractional ionization on the phase space have been discussed. SPIMOX can achieve high throughputs for thin-SOI structure fabrications using high fractional ionization plasmas. The phase space developed for SPIMOX implantation ran also be used for other high-dose dc implantations with PIII which require a peaked implant profile below the surface.

Separation of plasma implantation of oxygen to form silicon on insulator

Abstract: Separation by plasma implantation of oxygen (SPIMOX) is an economical method for silicon-on-insulator (SOI) wafer fabrication. This process employs the plasma immersion ion implantation (PIII) for the implantation of oxygen ions. The implantation rate, which is independent of the wafer size, is considerably higher than that of conventional implantation. The simpler implanter set-up is lower in cost and easier to maintain. The feasibility of SPIMOX has been demonstrated with successful fabrication of SOI structures implementing this process. The operational phase space on implantation condition, oxygen dose, and annealing requirement are identified. Secondary ion mass spectrometry analysis and cross-sectional transmission electron microscopy micrographs of the SPIMOX sample showed continuous buried oxide under single crystal overlayer with sharp silicon/oxide interfaces.

Characterization of contact and via failure under short duration high pulsed current stress

Abstract: Contact and via failure under short-duration, high current pulses has been characterized for the first time. It is shown that the critical current is strongly dependent on the pulse width, and contact/via cross section area. It is also found that for contact structures the critical current depends on the thermal conductivity of the underlying diffusion region and is independent of the electrical properties such as sheet resistance. Further, it is shown that single Al contacts can sink similar currents as compared to W contacts, and multiple W/Al contact structures will fail under smaller current density as a result of lower heat dissipation capacity. The effect gets stronger with thicker contact liner metal. Critical current density is also found to be decreasing with increasing number of vias due to lower heat dissipating capacity of multiple vias. Furthermore, the contact/via failure thresholds were found to be independent of the direction of electron flow. The contact breakdown mechanism has been shown to be related to the TiN-TiSi/sub 2/ interface reaction which causes a sudden increase in contact resistance. The via failure mechanism has been shown to be due to thermal runaway resulting in a complete destruction of the structures.

Characteristics of GaAs and AlGaAs homojunction avalanche photodiodes with thin multiplication regions

Abstract: The gain and noise of thin GaAs and Al0.2Ga0.8As homojunction avalanche photodiodes were measured. The gain and the excess noise factor were found to be significantly lower than would be expected using ionization coefficients reported in the literature. The discrepancy is believed to be due to physical effects that become significant in thin multiplication layers. It is shown that the gain and excess noise under electron injection can be accurately fit using conventional models with width-dependent ionization coefficients.

Realistic worst-case circuit simulation system and method

Abstract: A system and method of simulating operation of an integrated circuit. First, circuit characteristics of circuit components are measured, and a set of circuit simulation model parameters are generated for each measured circuit component. Then, the operation of predefined circuit primitives is simulated using each of the generated sets of circuit simulation model parameters. The circuit primitives include the measured circuit components. The simulated operations are then analyzed to select ones of the simulated operations that are worst, best and nominal with respect to a specified circuit performance parameter and to extract model parameters corresponding to the worst case, best case and nominal case sets of circuit simulation model parameters from the generated sets of circuit simulation model parameters. Each extracted set of circuit simulation model parameters comprises one of the generated sets of circuit simulation model parameters. Then a target circuit is simulated using each of the worst case, best case and nominal case sets of circuit simulation model parameters so as to generate data representing the target circuits under worst case, best case and nominal case manufacturing conditions.

Experimental confirmation of an accurate CMOS gate delay model for gate oxide and voltage scaling

Abstract: MOSFET's and CMOS ring oscillators with gate oxide thicknesses from 2.58 nm to 5.7 nm and effective channel lengths down to 0.21 /spl mu/m have been studied at voltages from 1.5 V to 3.3 V. Physical and electrical measurement of gate oxide thicknesses are compared. Ring oscillators' load capacitance is characterized through dynamic current measurement. An accurate model of CMOS gate delay is compared with measurement data. It shows that the dependence of gate propagation delay on gate oxide, channel length, and voltage scaling can be predicted.

Plasma Charging Damage On Ultra-thin Gate Oxides

Abstract: Capacitor and threshold voltage and sub- threshold swing of MOSFET's with gate oxide thickness varying from 2.2 to 7.7 nm are analyzed to study the plasma charging damage by the metal etching process. Surprisingly, the ultrathin gate oxide has better immunity to plasma charging damage than the thicker oxide, thanks to the excellent tolerance of the thin gate oxide to tunneling current. This finding has very positive implications for the prospect of manufacturable scaling of gate oxide to very thin thickness.

High field hole velocity and velocity overshoot in silicon inversion layers

Abstract: We report measurements of the drift velocity of holes in silicon inversion layers. The saturation velocity of holes at 300 K is found to be strongly dependent on the effective vertical field. No hole velocity overshoot was observed down to 0.16 /spl mu/m channel length at room temperature. At 77 K, hole velocity saturation is much less pronounced, and a 10% higher average velocity is observed for 0.16 /spl mu/m channel length as compared to 0.36 /spl mu/m channel length.

AC output conductance of SOI MOSFETs and impact on analog applications

Abstract: We report a frequency-dependent output conductance of partially depleted SOI MOSFETs. For high-frequency analog applications, the output conductance is less than half and the dynamic range of V/sub d/ is two times higher than the dc I-V characteristics would indicate. A simple physical model for the phenomenon that involves a phenomenological body charging capacitance and can fit data within 10% is presented.

Temperature and current effects on small-geometry-contact resistance

Abstract: The effects of temperature and current on the resistance of small geometry silicided contact structures have been characterized and modeled for the first time Both, temperature and high current induced self heating have been shown to cause contact resistance lowering which can be significant in the performance of advanced ICs It is demonstrated that contact-resistance sensitivity to temperature and current is controlled by the silicide thickness which influences the interface doping concentration, N Behavior of W-plug and force-fill (FF) Al plug contacts have been investigated in detail A simple model has been formulated which directly correlates contact resistance to temperature and N Furthermore, thermal impedance of these contact structures have been extracted and a critical failure temperature demonstrated that can be used to design robust contact structures

Impact of nitrogen (N/sub 14/) implantation into polysilicon gate on high-performance dual-gate CMOS transistors

Abstract: The effect of nitrogen (N/sub 14/)implant into dual-doped polysilicon gates was investigated. The electrical characteristics of sub-0.25-/spl mu/m dual-gate transistors (both p- and n-channel), MOS capacitor quasi-static C-V curve, SIMS profile, poly-Si gate R/sub s/, and oxide Q/sub bd/ were compared at different nitrogen dose levels. A nitrogen dose of 5/spl times/10/sup 15/ cm/sup -2/ is the optimum choice at an implant energy of 40 KeV in terms of the overall performance of both p- and n-MOSFETs and the oxide Q/sub bd/. The suppression of boron penetration is confirmed by the SIMS profiles to be attributed to the retardation effect in bulk polysilicon with the presence of nitrogen. High nitrogen dose (1/spl times/10/sup 16/ cm/sup -2/) results in poly depletion and increase of sheet resistance in both unsilicided and silicided p/sup +/ poly, degrading the transistor performance. Under optimum design, nitrogen implantation into poly-Si gate is effective in suppressing boron penetration without degrading performance of either p- or n-channel transistors.

AC Charge Centroid Model For Quantization Of Inversion Layer In N-MOSFET

Abstract: A simulator using coupled Schrodinger equation, Poisson equation and Fermi-Dirac statistics to analyze inversion layer quantization is verified with the measured C-V data of thin oxide MOS capacitors closely. The effects of bias voltage, oxide thickness and doping concentration on the AC charge centroid is presented. A simple empirical model for the AC charge centroid of the inversion layer is proposed. An effective AC thickness is introduced to model the inversion capacitance in both weak and strong inversion regime. This model predlcts the inversion layer capacitance and AC charge centroid in term of Tm, V , , and V, explicitly. Introduction As MOSFETs are scaled to deep sub-micron Qmension, the oxide thickness is correspondingly reduced. In the thin oxide regime (< lOnm) , the effect of channel quantization is increasingly important. Many studies have been presented on the effect of quantization on MOSFET's performance and characterization [1,2]. In the thin oxide regime, a better quantitative understanding of MOS capacitance is increasingly important. Classical model for solving the inversion charge distribution predicts that the charge peaks at the intedace and overestimates the capacitance. Conventional method of oxide thckness estimation using C-V measurement without includtng quantization of the inversion layer results in a higher value of oxide thickness, the electrical thickness. Several correction methods were proposed [3,4], however, these studies lack universal quantitative expression for the correction term. It is known that due to the quantization of the inversion layer, the peak of the charge may be tens of angstroms away from the interface, contrary to the classical solution which suggests that the peak charge density is right at the Si/Si02 surface. Approximate theoretical solution of the Schrodinger and Poisson equations for the average position 11 -A (Q, +--?,) 3[5,6]. However there is no simple analytical model to quantitatively predict the average charge location. In this work, we developed a 1Dimensional simulator that self-consistently solves Schrodinger and Poisson equations and Fermi-Dirac Statistics. We propose an empirical model from the simulation results that can express the AC charge centroid, X , , due to quantization by V,, V,, T, explicitly. Using this simple model, the correction term can be easily applied in engineering practices and to circuit simulation models. suggests X d c -

Investigation of interconnect capacitance characterization using charge-based capacitance measurement (CBCM) technique and 3-D simulation

Abstract: This paper examines the recently introduced Charge-Based Capacitance Measurement (CBCM) technique through use of a 3-D interconnect simulator. This method is shown to have several advantages over extensive computer simulation in determining parasitic interconnect capacitances, which are the dominant source of delay in modern circuits. Metal to substrate, interwire, and interlayer capacitances are each discussed and overall close agreement is found between CBCM and 3-D simulation. Full process interconnect characterization is one possible application of this new compact, high-resolution test structure.

Velocity overshoot of electrons and holes in Si inversion layers

Abstract: Velocity overshoot of inversion layer electrons and holes is studied experimentally and analytically in special test structures with nominally uniform electric field. The data were used to calibrate energy relaxation parameters in a commercial simulator MEDICI ver. 2.0. We propose an analytical model for velocity overshoot and show that it agrees well with experimental data. The amount of hole velocity overshoot is small.