Showing papers by "Chenming Hu published in 1999"

Sub 50-nm FinFET: PMOS

Abstract: High performance PMOSFETs with gate length as short as 18-nm are reported. A self-aligned double-gate MOSFET structure (FinFET) is used to suppress the short channel effect. A 45 nm gate-length PMOS FinEET has an I/sub dsat/ of 410 /spl mu/A//spl mu/m (or 820 /spl mu/A//spl mu/m depending on the definition of the width of a double-gate device) at Vd=Vg=1.2 V and Tox=2.5 nm. The quasi-planar nature of this variant of the double-gate MOSFETs makes device fabrication relatively easy using the conventional planar MOSFET process technologies. Simulation shows possible scaling to 10-nm gate length.

MOS capacitance measurements for high-leakage thin dielectrics

Abstract: As oxide thickness is reduced below 2.5 nm in MOS devices, both series and shunt parasitic resistances become significant in capacitance-voltage (C-V) measurements. A new technique is presented which allows the frequency-independent device capacitance to be accurately extracted from impedance measurements at two frequencies. This technique is demonstrated for a 1.7 nm SiO/sub 2/ capacitor.

A new look at impact ionization-Part II: Gain and noise in short avalanche photodiodes

Abstract: For Part I see R.J. McIntyre, ibid., vol.46, no.8, pp.1623-31 (1999). In Part I, a new theory for impact ionization that utilizes history-dependent ionization coefficients to account for the nonlocal nature of the ionization process has been described. In this paper, we will review this theory and extend it with the assumptions that are implicitly used in both the local-field theory in which the ionization coefficients are functions only of the local electric field and the new one. A systematic study of the noise characteristics of GaAs homojunction avalanche photodiodes with different multiplication layer thicknesses is also presented. It is demonstrated that there is a definite "size effect" for thin multiplication regions that is not well characterized by the local-field model. The new theory, on the other hand, provides very good fits to the measured gain and noise. The new ionization coefficient model has also been validated by Monte Carlo simulations.

On thermal effects in deep sub-micron VLSI interconnects

Abstract: This paper presents a comprehensive analysis of the thermal effects in advanced high performance interconnect systems arising due to self-heating under various circuit conditions, including electrostatic discharge. Technology (Cu, low-k etc.) and scaling effects on the thermal characteristics of the interconnects, and on their electromigration reliability has been analyzed simultaneously, which will have important implications for providing robust and aggressive deep sub-micron interconnect design guidelines. Furthermore, the impact of these thermal effects on the design (driver sizing) and optimization of the interconnect length between repeaters at the upper-level signal lines are investigated.

MOSFET Modeling and BSIM3 User's Guide

Abstract: From the Publisher: MOSFET Modeling & BSIM3 User's Guide explains the detailed physical effects that are important in modeling MOSFETs, and presents the derivations of compact model expressions so that users can understand the physical meaning of the model equations and parameters.. "The book is written for circuit designers, device engineers as well as device scientists worldwide. It is also suitable as a reference for graduate courses and courses in circuit design or device modeling. Furthermore, it can be used as a textbook for industry courses devoted to BSIM3.

A unified gate oxide reliability model

Abstract: Existing literature indicates that there are two major mechanisms involved in the time dependent dielectric breakdown (TDDB) of silicon dioxide, and each mechanism dominates under different stress conditions. We suggest that the thermochemical (linear E) model and the hole-induced (1/E) model can be unified in one model. Based on the unified model, a wide range of TDDB data from different sources were examined and shown to behave consistently. Temperature and stress field dependencies are treated together in the model so that the lifetime is a single-valued function of temperature and field. The criterion for screen/ramp breakdown test is also discussed with the model. Furthermore, the unified model accounts for the effect of gross defects, which limit the oxide reliability in real ICs. The model is be used to predict the 10-year lifetime breakdown field or acceptable oxide thickness for a given voltage, and results suggest that further refinements for thin oxide (<5 nm) are necessary.

Method of separating films from bulk substrates by plasma immersion ion implantation

Abstract: A technique for fabricating substrates such as a silicon-on-insulator substrate using a plasma immersion ion implantation ("PIII") system 10. The technique includes a method, which has a step of providing a substrate 2100. Ions are implanted 2109 into a surface of the substrate to a first desired depth to provide a first distribution of the ions using a plasma immersion ion implantation system 10. The implanted ions define a first thickness of material 2101 above the implant. Global energy is then increased of the substrate to initiate a cleaving action, where the cleaving action is sufficient to completely free the thickness of material from a remaining portion of the substrate. By way of the PIII system, the ions are introduced into the substrate in an efficient and cost effective manner.

Ultra-thin body SOI MOSFET for deep-sub-tenth micron era

Abstract: A 40nm-gate-length ultra-thin body (UTB) nMOSFET is demonstrated. A self-aligned thin body SOI device has previously been proposed for suppressing the short channel effect. UTB structure can eliminate the punchthrough path between source and drain and provide a more evolutionary alternative to the double-gate MOSFET for deep-sub-tenth micron technology. The advantage of using UTB is illustrated through device simulation (with the aid of Silvaco ATLAS) using simple doping profiles for the body and S/D (simple Gaussian).

Modeling of pocket implanted MOSFETs for anomalous analog behavior

Abstract: Pocket implant is widely used in deep-sub-micron CMOS technologies to combat short channel effects It, however, brings anomalously large drain-induced threshold voltage shift and low output resistance to long channel devices This creates a serious problem for high-performance analog circuits In this paper, the first physical model of these effects is proposed and verified against data from a 018 /spl mu/m technology This model is suitable for SPICE modeling

Dynamic threshold pass-transistor logic for improved delay at lower power supply voltages

Abstract: We have investigated circuit options to surpass the 1 V power-supply limitation predicted by traditional scaling guidelines. By modulating the body bias, we can dynamically adjust the threshold voltage to have different on- and off-state values. Several dynamic threshold voltage MOSFET (DTMOS) logic styles were analyzed for ultralow-power use-from 1.5 down to 0.5 V. Since ordinary pass-transistor logic degrades as the voltages are reduced, we investigated the effects that a dynamic threshold has on various styles of pass-transistor logic. Three different pass-transistor restoration schemes were simulated with the various DTMOS techniques. Results indicate that controlling the body bias can provide a substantial speed increase and that such techniques are useful over a large range of supply voltages. Process complexity and other tradeoffs associated with DTMOS logic variations are also discussed.

Quantum effect in oxide thickness determination from capacitance measurement

Abstract: Simple quantitative models of charge displacement due to the quantum effect and its influence on gate oxide thickness measurements are presented. An effective oxide thickness (T/sub DC/) is introduced which is relevant to MOSFET current modeling. Physical oxide thickness and T/sub DC/ can be extracted easily from capacitance measurement, and the electrical thickness can be predicted from a target physical thickness using these new models.

Scaling effect on electromigration in on-chip Cu wiring

Abstract: Electromigration in on-chip plated Cu damascene interconnections has been investigated for metal line widths from 0.24 /spl mu/m to 1.3 /spl mu/m. Void growth at the cathode end and protrusions at the anode end of the lines have been found to be the main causes of failure. The failure lifetime was found to decrease linearly with decrease in the cross-sectional area of the line. This behavior can be explained by interface diffusion as the dominant path for transport and by the bamboo-like nature of the microstructure. The factor of n for the lifetime dependence on current density for 0.28 /spl mu/m wide lines, /spl tau/=/spl tau//sub 0/j/sup -n/, was found to increase from 1 to 2 as j increased beyond 25 mA//spl mu/m/sup 2/.

Self-heating characterization for SOI MOSFET based on AC output conductance

Abstract: A simple and accurate characterization method for the self-heating effect in SOI MOSFET is reported for the first time. The AC output conductance at one bias point and several frequencies are measured to determine the thermal resistance (R/sub th/) and thermal capacitance (C/sub th/) associated with SOI devices. The proposed methodology is critical for removing the misleadingly large self-heating effect from the DC I-V data in device modeling.

A long-refresh dynamic/quasi-nonvolatile memory device with 2-nm tunneling oxide

Abstract: A memory device using silicon rich oxide (SRO) as the charge trapping layer for dynamic or quasi-nonvolatile memory application is proposed. The device achieved write and erase speed at low voltage comparable to that of a dynamic-random-access memory (DRAM) cell with a much longer data retention time. This device has a SRO charge trapping layer on top of a very thin tunneling oxide (<2 nm). Using the traps in the SRO layer for charge storage, a symmetrical write/erase characteristics were achieved. This new SRO cell has an erase time much shorter than values of similar devices reported in the literature.

An efficient and accurate compact model for thin-oxide-MOSFET intrinsic capacitance considering the finite charge layer thickness

Abstract: As the gate oxide thickness is vigorously scaled down, quantization-induced charge layer thickness in MOSFETs has to be considered for accurate MOSFET intrinsic capacitance modeling for circuit simulation. We report in this paper an analytical MOSFET intrinsic capacitance model incorporating the concept of charge layer thickness, which was developed based on the self-consistent solution of the Schrodinger and Poisson equations with Fermi-Dirac statistics. The results demonstrate that this model has excellent accuracy and simulation performance.

Impact of time dependent dielectric breakdown and stress-induced leakage current on the reliability of high dielectric constant (Ba,Sr)TiO/sub 3/ thin-film capacitors for Gbit-scale DRAMs

Abstract: Time dependent dielectric breakdown (TDDB) and stress-induced leakage current (SILC) are investigated for the reliability of (Ba,Sr)TiO/sub 3/ (BST) thin films. Both time to breakdown (T/sub BD/) versus electric field (E) and T/sub BD/ versus 1/E plots show universal straight lines, independent of the film thickness, and predict lifetimes longer than 10 y at +1 V for 50 nm BST films with an SiO/sub 2/ equivalent thickness of 0.70 nm. SILC is observed at +1 V after electrical stress of BST films; nevertheless, 10 y reliable operation for Gbit-scale DRAMs is predicted in spite of charge loss by SILC. Lower (Ba+Sr)/Ti ratio is found to be strongly beneficial for low leakage, low SILC, long TBD, and therefore greater long-term reliability. This suggests a worthwhile tradeoff against the dielectric constant, which peaks at a (Ba+Sr)/Ti ratio of 1.05.

Evidence of hole direct tunneling through ultrathin gate oxide using P/sup +/ poly-SiGe gate

Abstract: P/sup +/ poly-Si and poly-Si/sub 0.75/Ge/sub 0.25/-gated PMOS transistors with ultrathin gate oxides of 25 and 29 /spl Aring/ were used for this study. The difference in the gate work function was used to determine the mechanisms of gate tunneling current in such thin gate oxides, Under negative gate bias (inversion bias), it was found that the source/drain terminal serves as a source of holes for small V/sub g/ value, and as gate bias increases (more negative), it becomes a hole sink. These observations can be interpreted in terms of two competing mechanisms. For the first time, hole direct tunneling is reported, Hole direct tunneling is the dominant mechanism for -2 V

Silicon nanoelectronics for the 21st century

Abstract: The advancement of device technology and the growth of the electronics market were intertwined in the past and probably will continue to be in the future. This observation suggests a new approach to predicting the potentials and the limitations of the scaling of MOSFETs using both technological and economic considerations. It is proposed that silicon CMOS technology can serve the electronics needs of at least most of the 21st century. This analysis also provides a backdrop for evaluating the need for unconventional devices. One current effort to develop 25 nm MOSFETs is described. There appear to be many opportunities and challenges in finding novel device structures and new processing techniques, and in understanding the physics of future devices.

Circuit performance variability decomposition

Abstract: In this paper, circuit performance variability composition is analyzed. Traditionally, the device variability has been the dominant source. It is believed that with continuing technology scaling into the deep sub-micron regime, the interconnect constitutes an increasing portion of the overall circuit delay, and variability. In this paper, we analytically investigate the delay variability composition for an advanced 0.18 /spl mu/m CMOS technology, accounting for the significant intra-field variability. A more realistic model to estimate the variance of global interconnect lines is proposed. The results indicate that the device variability of good designs contributes about 90% of the overall variability.

Direct sampling methodology for statistical analysis of scaled CMOS technologies

Abstract: The continued scaling of CMOS technologies introduces new difficulties to statistical circuit analysis and invalidates many of the methodologies developed earlier. The analysis of device parameter distributions reveals multiple sources of parameter correlations, some of which exhibit mutually opposing trends. We found that applying principal component analysis (PCA) to such heterogeneous statistical data may lead to confounding of data and result in underestimation of the total parameter variance. This imposes considerable constraints on the use of several methods of statistical circuit analysis based on PCA. Also the highly nonlinear relationships between the device parameters become more pronounced and cannot be approximated as linear even in the differential range. As a result, the response surface models based on the linear expansion of the performance variable around the nominal point of the device model parameters may lead to significant prediction errors. To address these difficulties, we propose a conceptually simple and accurate approach of direct sampling that treats the extracted SPICE parameter sets and their physical locations as an inseparable set and thus bypasses the dangerous stage of statistical inferences. We illustrate the methodology by applying it to the statistical analysis of a production CMOS process.

Enhancement of PMOS device performance with poly-SiGe gate

Abstract: Poly-Si and poly-Si/sub 0.75/Ge/sub 0.25/-gated PMOS transistors with a very thin gate oxide of 29 /spl Aring/ were fabricated. In addition to reduced gate-depletion effect (GDE) and reduced boron penetration, more favorable I/sub d/-V/sub d/ characteristics were observed for the poly-SiGe-gated transistors than poly-Si-gated transistors. This and the underlying superior hole mobility are explained with a universal mobility model based on V/sub g/, T/sub ox/, V/sub th/ and V/sub th/. Both reduced GDE and superior hole mobility contribute to the enhanced performance.

Silicon nanoelectronics for the 21st century

Abstract: The advancement of device technology and the growth of the electronics market were intertwined in the past and probably will continue to be in the future. This observation suggests a new approach to predicting the potentials and the limitations of the scaling of MOSFETs using both technological and economic considerations. It is proposed that silicon CMOS technology can serve the electronics needs of at least most of the 21st century. This analysis also provides a backdrop for evaluating the need for unconventional devices. One current effort to develop 25 nm MOSFETs is described. There appear to be many opportunities and challenges in finding novel device structures and new processing techniques, and in understanding the physics of future devices.

Intra-field gate CD variability and its impact on circuit performance

Abstract: Statistical analysis of an advanced CMOS process reveals a significant systematic within-field variability of gate CD strongly dependent on the local layout patterns We present a novel modeling methodology for accurate prediction of the effect of such CD variability on circuit performance that enables statistical design for increased performance and yield We also propose a mask-level gate CD correction algorithm allowing significant reduction of overall variability and provide a model to evaluate the effectiveness of correction

Performance and reliability comparison between asymmetric and symmetric LDD devices and logic gates

Abstract: The performance and reliability of NMOSFET asymmetric lightly doped drain (LDD) devices (with no LDD on the source side) are compared with those of conventional LDD devices. At a fixed V/sub dd/, asymmetric LDD devices exhibit higher I/sub dsat/ and shorter hot-carrier lifetime. To maintain the same hot-carrier lifetime, asymmetric LDD devices must operate at lower V/sub dd/ while higher I/sub dsat/ is retained. For the same hot-carrier lifetime, ring oscillators with NMOSFET asymmetric LDD devices can achieve 5% (10% if PMOSFET also had asymmetric LDD) higher speed and 10% lower power. The hot-carrier reliability of inverter, NAND, and NOR structures with asymmetric and conventional LDD devices is also simulated and compared.

MOSFETs with 9 to 13 A thick gate oxides

Abstract: In this work, NMOSFETs with gate oxides between 9 to 13 A have been fabricated and its behavior analyzed. An improved methodology of extracting gate oxide thickness from the MOSFET gate currents in the accumulation regime is proposed. Experimental evidence for a mobility reduction mechanism, namely Remote Charge Scattering, has been presented. The mobility was found to be degraded because of scattering by ionized impurities in the poly-gate.

Modeling the impact of back-end process variation on circuit performance

Abstract: We present a stochastic approach to account for on-chip interconnect process variation. A Monte Carlo approach is taken using actual process distributions to generate realistic 3-D performance corners. Accurate analytical models are used to provide a >3 order of magnitude speedup over simulation techniques. Resulting delay and noise performance spreads are 33 to 63% tighter than those found using a conventional technique. We apply this method to a clock distribution network to more precisely determine clock skew.

Submicron CMOS thermal noise modeling from an RF perspective

Abstract: Continuous scaling of submicron CMOS technologies will soon make low cost, wireless system-on-a-chip communication products possible. The ultimate goal of these systems is to integrate the entire RF front-end with DSP together on a single chip. One key issue to the success of this CMOS RF system LSI chip implementation is how to accurately predict circuit performance using simulators such as SPICE. This will require accurate RF AC and noise models. The latter is essential for optimizing the noise performance which will in turn lead to a low power design. Recently, several CMOS RF models have been proposed for improvement on the accuracy of AC analysis at high frequencies (Ou et al, 1998). However, the accuracy of the existing noise models is not satisfactory for submicron CMOS. In this paper, a physics-based RF thermal noise model is proposed for submicron CMOS devices with a channel thermal noise model, resulting in a nearly bias-independent noise factor /spl gamma/. This model shows good agreement with measured RF noise data across a wide range of bias conditions.

Observation of reduced boron penetration and gate depletion for poly-Si/sub 0.8/Ge/sub 0.2/ gated PMOS devices

Abstract: Poly-Si/sub 0.8/Ge/sub 0.2/-and poly-Si-gated PMOS capacitors with very thin gate oxides were fabricated. Boron penetration and poly-gate depletion effects (PDE) in these devices were both analyzed. Observations of smaller flat-band voltage shift and superior gate oxide reliability suggest less boron penetration problem in poly-Si/sub 0.8/Ge/sub 0.2/-gated devices. Higher dopant activation rate, higher active dopant concentration near the poly/SiO/sub 2/ interface and therefore improved PDE were also found in boron-implanted poly-Si/sub 0.8/Ge/sub 0.2/-gated devices as compared to poly-Si-gated devices. A larger process window therefore exists for a poly-Si/sub 0.8/Ge/sub 0.2/ gate technology with regard to the tradeoff between boron penetration and poly-gate depletion.

Non-volatile memory device with true CMOS compatibility

Abstract: A low-cost non-volatile memory device using a standard CMOS process without additional processing steps is investigated for embedded applications. The cell consists of a PMOS transistor in which no electrical contact is made to the gate electrode and a series NMOS access transistor. Experimental data show that sufficient read current and disturb lifetime can be achieved. Data retention characteristics are also examined.