scispace - formally typeset
Search or ask a question

Showing papers by "Chenming Hu published in 2000"


Journal ArticleDOI
TL;DR: In this paper, a self-aligned double-gate MOSFET, FinFET was proposed by using boron-doped Si/sub 04/Ge/sub 06/ as a gate material.
Abstract: MOSFETs with gate length down to 17 nm are reported To suppress the short channel effect, a novel self-aligned double-gate MOSFET, FinFET, is proposed By using boron-doped Si/sub 04/Ge/sub 06/ as a gate material, the desired threshold voltage was achieved for the ultrathin body device The quasiplanar nature of this new variant of the vertical double-gate MOSFETs can be fabricated relatively easily using the conventional planar MOSFET process technologies

1,668 citations


Proceedings ArticleDOI
01 Jan 2000
TL;DR: A new paradigm of predictive MOSFET and interconnect modeling is introduced to specifically address SPICE compatible parameters for future technology generations and comparisons with published data and 2D simulations are used to verify this predictive technology model.
Abstract: A new paradigm of predictive MOSFET and interconnect modeling is introduced. This approach is developed to specifically address SPICE compatible parameters for future technology generations. For a given technology node, designers can use default values or directly input L/sub eff/, T/sub ok/, V/sub t/, R/sub dsw/ and interconnect dimensions to instantly obtain a BSIM3v3 customized model for early stages of circuit design and research. Models for 0.18 /spl mu/m and 0.13 /spl mu/m technology nodes with L/sub eff/ down to 70 nm are currently available on the web. Comparisons with published data and 2D simulations are used to verify this predictive technology model.

544 citations


Patent
23 Oct 2000
TL;DR: In this article, a planar MOSFET is fabricated in a silicon layer overlying an insulating layer (e.g., SIMOX) with the device extending from the insulating layers as a fin.
Abstract: A FinFET device is fabricated using conventional planar MOSFET technology. The device is fabricated in a silicon layer overlying an insulating layer (e.g., SIMOX) with the device extending from the insulating layer as a fin. Double gates are provided over the sides of the channel to provide enhanced drive current and effectively suppress short channel effects. A plurality of channels can be provided between a source and a drain for increased current capacity. In one embodiment two transistors can be stacked in a fin to provide a CMOS transistor pair having a shared gate.

534 citations


Proceedings ArticleDOI
01 Dec 2000
TL;DR: In this article, thin-body transistors with silicide source/drains were fabricated with gate-lengths down to 15 nm and complementary low-barrier silicides were used to reduce contact and series resistance.
Abstract: Thin-body transistors with silicide source/drains were fabricated with gate-lengths down to 15 nm. Complementary low-barrier silicides were used to reduce contact and series resistance. Minimum gate-length transistors with T/sub ox/=40 /spl Aring/ show PMOS |I/sub dsat/|=270 /spl mu/A//spl mu/m and NMOS |I/sub dsat/|=190 /spl mu/A//spl mu/m with V/sub ds/=1.5 V, |V/sub g/-V/sub t/|=1.2 V and, I/sub on//I/sub off/>10/sup 4/. A simple transmission model, fitted to experimental data, is used to investigate effects of oxide scaling and extension doping.

246 citations


Proceedings ArticleDOI
01 Dec 2000
TL;DR: In this article, an analytical intrinsic gate leakage model for MOSFET with physical source/drain current partition is developed, which has been implemented in BSIM4 and BSIM3.
Abstract: Gate dielectric leakage current becomes a serious concern as sub-20 /spl Aring/ gate oxide prevails in advanced CMOS processes Oxide this thin can conduct significant leakage current by various direct-tunneling mechanisms and degrade circuit performance While the gate leakage current of MOS capacitors has been much studied, little has been reported on compact MOSFET modeling with gate leakage In this work, an analytical intrinsic gate leakage model for MOSFET with physical source/drain current partition is developed This model has been implemented in BSIM4

205 citations


Journal ArticleDOI
TL;DR: In this paper, a 40nm-gate-length ultrathin-body (UTB) nMOSFET is presented with 20-nm body thickness and 2.4-nm gate oxide.
Abstract: A 40-nm-gate-length ultrathin-body (UTB) nMOSFET is presented with 20-nm body thickness and 2.4-nm gate oxide. The UTB structure eliminates leakage paths and is an extension of a conventional SOI MOSFET for deep-sub-tenth micron CMOS. Simulation shows that the UTB SOI MOSFET can be scaled down to 18-nm gate length with <5 nm UTB. A raised poly-Si S/D process is employed to reduce the parasitic series resistance.

202 citations


Proceedings ArticleDOI
01 Dec 2000
TL;DR: In this article, the scaling issues of double-gate MOSFETs are explored in the nanoscale regime and the advantages of using alternative channel materials to facilitate scaling are investigated.
Abstract: In the nanoscale regime, the double-gate MOSFET can provide superior short-channel behavior. For this structure, device scaling issues are explored. Gate length scaling will be limited by the ability to control off-state leakage current due to quantum tunneling and thermionic emission between the source and drain as well as band-to-band tunneling between the body and drain. Lateral S/D doping abruptness requirements for gate length scaling are examined. V/sub T/ control will be challenging as a single gate material for both NMOS and PMOS devices cannot provide low yet symmetrical V/sub T/'s. CMOS integration will thus require dual gate workfunction tuning, channel doping, or asymmetrical double-gates to adjust V/sub T/. Advantages of using alternative channel materials to facilitate scaling are investigated.

173 citations


Journal ArticleDOI
TL;DR: In this paper, the authors present a study on the characterization and modeling of direct tunneling gate leakage current in both N and P-type MOSFETs with ultrathin silicon nitride (Si/sub 3/N/sub 4/) gate dielectric formed by the jet-vapor deposition (JVD) technique.
Abstract: We present a study on the characterization and modeling of direct tunneling gate leakage current in both N- and P-type MOSFETs with ultrathin silicon nitride (Si/sub 3/N/sub 4/) gate dielectric formed by the jet-vapor deposition (JVD) technique. The tunneling mechanisms in the N- and PMOSFETs were clarified. The electron and hole tunneling masses and barrier potentials for the different tunneling mechanisms mere extracted from measured data using a new semi-empirical model. This model was used to project the scaling limits of the JVD Si/sub 3/N/sub 4/ gate dielectric based on the supply voltages for the various technology nodes and the maximum tolerable direct tunneling gate current for high-performance and low-power applications.

164 citations


Proceedings ArticleDOI
05 Nov 2000
TL;DR: A location-dependent timing analysis methodology is proposed that allows to mitigate the detrimental effects of Lgate variability, and a tool linking the layout-dependent spatial information to circuit analysis is developed, which allows estimating performance degradation for the given circuit and process parameters.
Abstract: Using data collected from an actual state-of-the-art fabrication facility, we conducted a comprehensive characterization of an advanced 0.18 /spl mu/m CMOS process. The measured data revealed significant systematic, rather than random, spatial intra-chip variability of MOS gate length, leading to large circuit path delay variation. The critical path value of a combinational logic block varies by as much as 17%, and the global skew is increased by 8%. Thus, a significant timing error (/spl sim/25%) and performance loss takes place if variability is not properly addressed. We derive a model, which allows estimating performance degradation for the given circuit and process parameters. Analysis shows that the spatial, rather than proximity-dependent, systematic Lgate variability is the main cause of large circuit speed degradation. The degradation is worse for the circuits with a larger number of critical paths and shorter average logic depth. We propose a location-dependent timing analysis methodology that allows to mitigate the detrimental effects of Lgate variability, and developed a tool linking the layout-dependent spatial information to circuit analysis. We discuss the details of the practical implementation of the methodology, and provide the guidelines for managing the design complexity.

92 citations


Proceedings ArticleDOI
13 Jun 2000
TL;DR: In this paper, a model is proposed to quantify the tunneling currents through ultra-thin gate oxides, which can accurately predict the gate and substrate currents and all the subcomponents in dual-gate CMOS devices.
Abstract: A model is proposed to quantify the tunneling currents through ultra-thin gate oxides. With a proper set of effective mass and barrier height, this new model can accurately predict the gate and substrate currents and all the subcomponents in dual-gate CMOS devices. This model can also be employed to extract T/sub ox/ for thin oxide from I-V data with 0.1/spl Aring/ sensitivity, where C-V extraction can be difficult or impossible.

87 citations


Proceedings ArticleDOI
01 Jan 2000
TL;DR: In this paper, a novel sub-100 nm CMOS technology with strained-Si/sub 0.76/Ge/ sub 0.24/Si heterostructure channels formed by ultra-high-vacuum chemical-vapor-deposition (UHV-CVD) was presented.
Abstract: We report the demonstration of a novel sub-100 nm CMOS technology with strained-Si/sub 0.76/Ge/sub 0.24//Si heterostructure channels formed by ultra-high-vacuum chemical-vapor-deposition (UHV-CVD). The incorporation of 24% Ge in the channel provides a 25% enhancement in PMOSFET drive current for channel lengths down to 0.1 /spl mu/m. Enhancement in NMOSFET drive current is concomitantly observed for channel lengths below 0.4 /spl mu/m.

Journal ArticleDOI
TL;DR: In this article, the concept and demonstration of a nanoscale ultra-thin-body silicon on-insulator (SOI) P-channel MOSFET with a Si/sub 1-x/Ge/sub x/Si heterostructure channel was presented.
Abstract: We report the concept and demonstration of a nanoscale ultra-thin-body silicon on-insulator (SOI) P-channel MOSFET with a Si/sub 1-x/Ge/sub x//Si heterostructure channel. First, a novel lateral solid-phase epitaxy process is employed to form an ultra-thin-body that suppresses the short-channel effects. Negligible threshold voltage roll-off is observed down to a channel length of 50 nm. Second, a selective silicon implant that breaks up the interfacial oxide is shown to facilitate unilateral crystallization to form a single crystalline channel. Third, the incorporation of SiGe in the channel resulted in a 70% enhancement in the drive current.

Proceedings ArticleDOI
01 Jan 2000
TL;DR: In this article, a new model for leakage mechanism in tail-mode bits of DRAM data retention characteristics was proposed, where the root cause is electric field enhancement caused by metal precipitates located at the gate-drain overlap region.
Abstract: In this paper we propose a new model for leakage mechanism in tail-mode bits of DRAM data retention characteristics. For main-mode bits, leakage current can be attributed to junction thermal-generation leakage current. For tail-mode bits, it is found for the first time that Gate-Induced Drain Leakage (GIDL) current has a dominant impact. The root cause is electric field enhancement caused by metal precipitates located at the gate-drain overlap region.

Journal ArticleDOI
TL;DR: In this paper, an extension of the BSIM3v3 MOSFET model for small-signal radio-frequency circuit simulation is proposed and investigated, and detailed comparisons of the y and s parameters with both two-dimensional device simulations and measurement data are presented.
Abstract: An accurate and simple lumped-element extension of the BSIM3v3 MOSFET model for small-signal radio-frequency circuit simulation is proposed and investigated. Detailed comparisons of the small-signal y and s parameters with both two-dimensional device simulations and measurement data are presented. A procedure is developed to extract the values of two lumped resistors-the only added elements. The non-quasi-static and substrate effects can be modeled with these two resistors to significantly improve the model accuracy up to a frequency of 10 GHz, which is about 70% of the f/sub T/ of the 0.5 /spl mu/m NMOS transistor.

Proceedings ArticleDOI
19 Jun 2000
TL;DR: In this paper, a 60 nm planarized solid phase epitaxy (SPE) based MOSFET is proposed to suppress short channel effects such as DIBL and V/sub t/rolloff.
Abstract: The continuous scaling of MOSFET technology into the deep sub-micron regime poses considerable challenge to the conventional MOSFET structure. To suppress short-channel effects such as DIBL and V/sub t/ roll-off, extremely high levels of channel doping are required, but these result in increased leakage and degraded mobility. Simulation shows that the ultra-thin body MOSFET is a promising alternative structure that effectively suppresses DIBL and other short channel effects. The channel film thickness required is typically 30% of the gate length. The most difficult step for fabrication of the ultra-thin body FET is the formation of a uniform thin channel film. Oxidation and etch back have been proposed, but are limited by thickness uniformity of the starting SOI wafers and by process-induced variation. On the other hand, deposited films can be well controlled and have good uniformity, so finding ways to deposit highly uniform channel material is very plausible. Solid phase epitaxy (SPE) has been reported for fabrication of sub-100 nm devices (Subramanian et al, 1999). In SPE, the thin film is formed by lateral crystallization of an amorphous deposited silicon film, giving precise control over channel thickness. In this paper, 60 nm planarized SPEFETs with excellent performance are reported. The effect of different trench sizes is investigated. Both single sided and two sided crystallization on the channel film is also studied.

Proceedings ArticleDOI
05 Nov 2000
TL;DR: It is demonstrated, for example, that optimal wire sizing models need to consider inductive effects -- and that use of more accurate worst-case capacitive coupling noise switch factors substantially increases peak noise estimates compared to traditional {0,2} bounds.
Abstract: In this paper, we quantify the impact of global interconnect optimization techniques that address such design objectives as delay, peak noise, delay uncertainty due to noise, power, and cost. In doing so, we develop a new system-performance simulation model as a set of studies within the MARCO GSRC Technology Extrapolation (GTX) system. We model a typical point-to-point global interconnect and focus on accurate assessment of both circuit and design technology with respect to such issues as inductance, signal line shielding, dynamic delay, buffer placement uncertainty and repeater staggering. We demonstrate, for example, that optimal wire sizing models need to consider inductive effects -- and that use of more accurate {-1,3} worst-case capacitive coupling noise switch factors substantially increases peak noise estimates compared to traditional {0,2} bounds. We also find that optimal repeater sizes are significantly smaller than conventional models would suggest, especially when considering energy-delay issues.

Proceedings ArticleDOI
13 Jun 2000
TL;DR: Dual-metal gate CMOS devices with rapid-thermal chemical vapor deposited (RTCVD) Si/sub 3/N/sub 4/ gate dielectric were fabricated using a self-aligned process.
Abstract: Dual-metal gate CMOS devices with rapid-thermal chemical vapor deposited (RTCVD) Si/sub 3/N/sub 4/ gate dielectric were fabricated using a self-aligned process. The gate electrodes are Ti and Mo for the N- and P-MOSFET respectively. Carrier mobilities are comparable to that predicted by the universal mobility model for SiO/sub 2/. C-V characteristics show good agreement with a simulation that takes quantum-mechanical effects into account, and clearly display the advantage of metal over poly-Si gates.

Proceedings ArticleDOI
05 Jun 2000
TL;DR: In this paper, the integration of dual damascene copper with low-k dielectric at the 0.13 /spl mu/m technology node is described, and the integration is achieved while maintaining reliability standards.
Abstract: The integration of dual damascene copper with low-k dielectric at the 0.13 /spl mu/m technology node is described. Up to five levels of copper wiring at three different metal pitches is provided in a spin-on organic inter metal dielectric (SiLK/sup TM/ semiconductor dielectric. The Dow Chemical Co.). Additional global wiring levels in fluorosilicate glass (FSG) at two different relaxed metal pitches result in a total of up to eight levels of hierarchical wiring for enhanced BEOL performance. Successful integration was achieved while maintaining reliability standards. Development of new advanced unit processes was required to meet the challenges presented by this work. Patterning and passivation methodologies are discussed. A key feature of the integration scheme and material set reported is the resulting reduction in complexity compared to other proposed low-k integration alternatives for the current generation.

Journal ArticleDOI
TL;DR: In this paper, the authors presented ultra-thin body PMOS transistors with gate lengths down to 20 nm fabricated using a low-barrier silicide as the source and drain.

Proceedings ArticleDOI
01 Dec 2000
TL;DR: In this paper, the impact of inductive coupling on delay and noise is compared to capacitive effects in high-speed buses, showing that current-return paths are not strictly bounded by wide VDD/GND lines.
Abstract: Inductive and capacitive coupling effects for high-speed global interconnects are studied via simulation. The impact of inductive coupling on delay and noise is found to be comparable to capacitive effects in high-speed buses. The results indicate that current-return paths are not strictly bounded by wide VDD/GND lines, so that inductive coupling is only partially eliminated by using shield wires. Shielding strategies for noise- and delay-sensitive nets is proposed, considering worst-case switching patterns.

Proceedings ArticleDOI
01 Jan 2000
TL;DR: BSIMPD as discussed by the authors is a physics-based SPICE model for bridging deep-submicron CMOS designs using partially-depleted SOI technologies, which has been implemented in many circuit simulators.
Abstract: BSIMPD, a physics-based SPICE model, is developed for bridging deep-submicron CMOS designs using partially-depleted SOI technologies. Formulated on top of the industry-standard bulk-MOSFET model BSIM3v3 for a sound base of scalability and robustness, BSIMPD captures SOI-specific dynamic behaviors with its built-in floating-body, self-heating and body-contact models. A parameter-extraction strategy is demonstrated, and the simulation efficiency is studied. The model has been tested extensively within IBM on state-of-the-art high speed SOI technologies. It has been implemented in many circuit simulators.

Proceedings ArticleDOI
19 Jun 2000
TL;DR: In this article, an 8-nm ultra-thin-body (UTB) SOI was used for MOSFETs with selectively deposited Ge raised source/drain (S/D) implemented in 8 nm ultra thin-body SOI.
Abstract: MOSFETs with selectively deposited Ge raised source/drain (S/D) implemented in 8 nm ultra-thin-body (UTB) SOI are demonstrated. The Ge is selectively deposited by LPCVD and annealed at a low temperature using RTA (650/spl deg/C, 20 s). Devices with gate lengths down to 30 nm are obtained with 8 nm UTB and show excellent short-channel behavior.

Journal ArticleDOI
TL;DR: In this paper, the dependence of the work function of Mo on deposition and annealing conditions is investigated, and it is shown that the work functions of Mo can be varied over the range of 4.0-5.0V by a combination of suitable post-deposition implantation and annaling schemes.
Abstract: Molybdenum has several properties that make it attractive as a CMOS gate electrode material. The high melting point (∼2610°C) and low coefficient of thermal expansion (5×10−6/°C, at 20 °C) are well suited to withstand the thermal processing budgets normally encountered in a CMOS fabrication process. Mo is among the most conductive refractory metals and provides a significant reduction in gate resistance as compared with doped polysilicon. Mo is also stable in contact with SiO2 at elevated temperatures. In order to minimize short-channel effects in bulk CMOS devices, the gate electrodes must have work functions that correspond to Ec (NMOS) and Ev (PMOS) in Si. This would normally require the use of two metals with work functions differing by about 1V on the same wafer and introduce complexities associated with selective deposition and/or etching. In this paper, the dependence of the work function of Mo on deposition and annealing conditions is investigated. Preliminary results indicate that the work function of Mo can be varied over the range of 4.0-5.0V by a combination of suitable post-deposition implantation and annealing schemes. Mo is thus a promising candidate to replace polysilicon gates in deep sub-micron CMOS technology. Processing sequences which might allow the work function of Mo to be stabilized on either end of the Si energy band gap are explored.

Journal ArticleDOI
TL;DR: In this article, the steady state and dynamic thermal behavior of small geometry vias under sinusoidal and pulsed current stress was investigated using scanning Joule expansion microscopy (SJEM).
Abstract: Thermal characteristics of submicron vias strongly impact reliability of multilevel VLSI interconnects. The magnitude and spatial distribution of the temperature rise around a via are important to accurately estimate interconnect lifetime under electromigration (EM), which is temperature dependent. Localized temperature rise can cause stress gradients inside the via structures and can also lead to thermal failures under high current stress conditions, such as electrostatic discharge (ESD) events. This letter reports the first use of a novel thermometry technique, scanning Joule expansion microscopy, to study the steady state and dynamic thermal behavior of small geometry vias under sinusoidal and pulsed current stress. Measurement of the spatial distribution of temperature rise around a submicron via is reported with sub-0.1 /spl mu/m resolution, along with other thermal characteristics including the thermal time constant.

Journal ArticleDOI
TL;DR: In this paper, the authors report a set of data on the evolution of stress in thin-film metallization wires during the transient region of electromigration, indicating possible microstructural effects on local flux divergence even in the case of wide, nonbamboo wires.
Abstract: We report a set of data on the evolution of stress in thin-film metallization wires during the transient region of electromigration. The excellent strain sensitivity of the x-ray microbeam topography technique allows real-time, spatially resolved measurements at the lowest currents reported to date (1.0×104–1.4×105 A/cm2). While the steady-state results agree qualitatively with the Blech’s stress gradient model [I. A. Blech, J. Appl. Phys. 47, 1203 (1976)], the threshold-length product calculated from our data is about 2–3 times smaller than previously reported values. Stress evolution during the transient state displays local fluctuations which cannot be attributed to experimental errors, indicating possible microstructural effects on local flux divergence even in the case of wide, nonbamboo wires.

Proceedings ArticleDOI
01 Dec 2000
TL;DR: In this article, the authors used the MEDICI 2D device simulator to study off-state leakage current in NMOS DGFETs as a function of channel length, and the short-channel leakage behavior was explained by analyzing the change in the channel potential barrier.
Abstract: Double gate MOSFETs (DGFETs) in the sub-0.1 /spl mu/m regime are unlikely to use channel doping to set the threshold voltage, V/sub t/. Therefore, work function engineering is required to properly set V/sub t/. Asymmetric DGFETs use one n/sup +/ and one p/sup +/-poly gate to achieve a reasonable threshold voltage (Tanaka et al., 1994), whereas symmetric DGFETs use the same near-midgap material for both gates. This results in significantly different energy-band diagrams. The on-state drive currents in these two structures have been shown to be comparable to each other if off-state leakage currents are balanced; in the on-state, the asymmetric DGFET matches the inherent two-channel advantage of the symmetric DGFET with a single dynamic-threshold channel (Kim and Fossum, 1999). However, their short-channel effects should differ, since the two structures have different leakage paths. In this paper, the MEDICI 2D device simulator is used to study off-state leakage current in NMOS DGFETs as a function of channel length. The short-channel leakage behavior is explained by analyzing the change in the channel potential barrier.

Proceedings ArticleDOI
01 Jan 2000
TL;DR: In this paper, a set of novel models that relate the DCC to the coupling noise waveform were proposed for use in the timing margin design and accurate experimental determination of sub-nanosecond coupling noise.
Abstract: The delay-change curve (DCC) characterizes the variation of the interconnect delay due to coupling noise. This paper describes a set of novel models that relate the DCC to the coupling noise waveform. These models are targeted for use in the timing margin design and accurate experimental determination of sub-nanosecond coupling noise. The circuit structure, a set of measurements, the model equations, and the waveform extraction procedures are newly proposed. Evaluation results using a 0.25 /spl mu/m test chip are presented showing good agreement with SPICE simulations.

Proceedings ArticleDOI
01 Dec 2000
TL;DR: A 2/sup nd/ order distributed RLC waveform model that captures both delay and overshoot effects more accurately than previous 1/sup st/ order models and a new approach to decoupling a set of coupled RLC lines by examining current return paths.
Abstract: In this paper, we develop a 2/sup nd/ order distributed RLC waveform model that captures both delay and overshoot effects more accurately than previous 1/sup st/ order models We then present a new approach to decoupling a set of coupled RLC lines by examining current return paths Noise and delay results from this technique match SPICE for a wide range of input parameters

Journal ArticleDOI
TL;DR: In this article, the scaling limits of the double-gate MOSFET structure are explored, and the eventual scaling limit is determined by the ability to control off-state leakage due to quantum mechanical tunneling and thermionic emission between the source and drain.

Proceedings ArticleDOI
01 Dec 2000
TL;DR: Mo metal gate p-MOSFETs with several advanced gate dielectrics were fabricated and good device characteristics were obtained in all cases Thermodynamic stability of Mo on Si/sub 3/N/sub 4/, ZrO/sub 2/ and ZrSiO/Sub 4/ was verified by good carrier mobility agreement with the universal mobility model as mentioned in this paper.
Abstract: Mo metal gate p-MOSFETs with several advanced gate dielectrics were fabricated A suitable p-MOSFET work function was achieved and good device characteristics were obtained in all cases Thermodynamic stability of Mo on Si/sub 3/N/sub 4/, ZrO/sub 2/ and ZrSiO/sub 4/ was verified by good carrier mobility agreement with the universal mobility model