Showing papers by "Chenming Hu published in 2003"

Frequency-independent equivalent-circuit model for on-chip spiral inductors

Abstract: A wide-band physical and scalable 2-/spl Pi/ equivalent circuit model for on-chip spiral inductors is developed. Based on physical derivation and circuit theory, closed-form formulas are generated to calculate the RLC circuit elements directly from the inductor layout. The 2-/spl Pi/ model accurately captures R(f) and L(f) characteristics beyond the self-resonant frequency. Using frequency-independent RLC elements, this new model is fully compatible with both ac and transient analysis. Verification with measurement data from a SiGe process demonstrates accurate performance prediction and excellent scalability for a wide range of inductor configurations.

Extremely scaled silicon nano-CMOS devices

Abstract: Silicon-based CMOS technology can be scaled well into the nanometer regime. High-performance, planar, ultrathin-body devices fabricated on silicon-on-insulator substrates have been demonstrated down to 15-nm gate lengths. We have also introduced the FinFET, a double-gate device structure that is relatively simple to fabricate and can be scaled to gate lengths below 10 nm. In this paper, some of the key elements of these technologies are described, including sublithographic patterning, the effects of crystal orientation and roughness on carrier mobility, gate work function engineering, circuit performance, and sensitivity to process-induced variations.

Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors

Abstract: In accordance with a preferred embodiment of the present invention, a silicon-on-insulator (SOI) chip includes a silicon layer of a predetermined thickness overlying an insulator layer. A multiple-gate fully-depleted SOI MOSFET including a strained channel region is formed on a first portion of the silicon layer. A planar SOI MOSFET including a strained channel region formed on another portion of the silicon layer. For example, the planar SOI MOSFET can be a planar fully-depleted SOI (FD-SOI) MOSFET or the planar SOI MOSFET can be a planar partially-depleted SOI (PD-SOI) MOSFET.

Structure and method of a strained channel transistor and a second semiconductor component in an integrated circuit

Abstract: A semiconductor chip includes a semiconductor substrate 126, in which first and second active regions are disposed. A resistor 124 is formed in the first active region and the resistor 124 includes a doped region 128 formed between two terminals 136. A strained channel transistor 132 is formed in the second active region. The transistor includes a first and second stressor 141, formed in the substrate oppositely adjacent a strained channel region 143.

MOSFET gate leakage modeling and selection guide for alternative gate dielectrics based on leakage considerations

Abstract: In this paper, we explore the scaling limits of alternative gate dielectrics based on their direct-tunneling characteristics and gate-leakage requirements for future CMOS technology generations. Important material parameters such as the tunneling effective mass are extracted from the direct-tunneling characteristics of several promising high-/spl kappa/ gate dielectrics for the first time. We also introduce a figure-of-merit for comparing the relative advantages of various gate dielectrics based on the gate-leakage current. Using an accurate direct-tunneling gate-current model and specifications from the International Technology Roadmap for Semiconductors (ITRS), we provide guidelines for the selection of gate dielectrics to satisfy the projected off-state leakage current requirements of future high-performance and low-power technologies.

Semiconductor nano-rod devices

Abstract: In a method of manufacturing a semiconductor device, a semiconductor layer is patterned to form a source region, a channel region, and a drain region in the semiconductor layer. The channel region extends between the source region and the drain region. Corners of the channel region are rounded by annealing the channel region to form a nano-rod structure. Part of the nano-rod structure is then used as a gate channel. Preferably, a gate dielectric and a gate electrode both wrap around the nano-rod structure, with the gate dielectric being between the nano-rod structure and the gate electrode, to form a transistor device.

Process-strained Si (PSS) CMOS technology featuring 3D strain engineering

Abstract: We report the demonstration of a process-strained Si (PSS) CMOS technology using the concept of three-dimensional (3D) strain engineering Methods of producing PSS include stress engineering of trench isolation, silicide, and cap layer, to improve NMOS and PMOS performance simultaneously Each of these approaches results in a 5-10% enhancement in the ring oscillator (RO) speed By taking advantage of preferential 3D strain engineering via one or combining more PSS techniques, CMOS performance can be further improved PSS is a cost effective technology for meeting CMOS power-performance requirements

Strained-channel transistor and methods of manufacture

Abstract: A semiconductor device includes a region of semiconductor material with first and second isolation trenches formed therein. The first isolation trench is lined with a first material having a low oxygen diffusion rate and is filled with an insulating material. The second isolation trench is not lined with the first material but is filled with an insulating material. A first transistor is formed adjacent the first isolation region and a second transistor formed adjacent the second isolation region.

Device with low-k dielectric in close proximity thereto and its method of fabrication

Abstract: A semiconductor device with a low-k material in close proximity thereto and its fabrication method. The device includes a gate electrode overlying a substrate. An electrically conductive plug is provided immediately adjacent to the gate electrode and making electrical contact to the device. A low-k dielectric material is disposed in the space between the gate electrode and the electrically conductive plug whereby reducing the parasitic capacitance. Thus, higher density of devices can be formed without decreasing operating speed.

A capacitorless double gate DRAM technology for sub-100-nm embedded and stand-alone memory applications

Abstract: A capacitorless, asymmetric double gate DRAM (DG-DRAM) technology is presented. Its double gate, thin body structure reduces dopant fluctuation effects, off-state leakage, and disturb problems. The cell's large body coefficient amplifies small gains of body potential into increased drain current. Experimental measurements of DG-DRAM were made using recessed channel SOI n-MOSFETs. No significant degradation in programming, retention, and read behavior was observed after 10/sup 11/ cycles. Cell geometry, operating voltages, and material quality should be considered for DG-DRAM in embedded and stand-alone applications. The feasibility of DG-DRAM in future high density CMOS memories depends on issues such as manufacturability, soft error reliability, and tail bit distribution.

Strained-channel transistor structure with lattice-mismatched zone

Abstract: A strained-channel transistor structure with lattice-mismatched zone and fabrication method thereof. The transistor structure includes a substrate having a strained channel region, comprising a first semiconductor material with a first natural lattice constant, in a surface, a gate dielectric layer overlying the strained channel region, a gate electrode overlying the gate dielectric layer, and a source region and drain region oppositely adjacent to the strained channel region, with one or both of the source region and drain region comprising a lattice-mismatched zone comprising a second semiconductor material with a second natural lattice constant different from the first natural lattice constant.

Multiple-gate transistors formed on bulk substrates

Abstract: In one aspect, the present invention teaches a multiple-gate transistor 130 that includes a semiconductor fin 134 formed in a portion of a bulk semiconductor substrate 132. A gate dielectric 144 overlies a portion of the semiconductor fin 134 and a gate electrode 146 overlies the gate dielectric 144. A source region 138 and a drain region 140 are formed in the semiconductor fin 134 oppositely adjacent the gate electrode 144. In the preferred embodiment, the bottom surface 150 of the gate electrode 146 is lower than either the source-substrate junction 154 or the drain-substrate junction 152.

Strained channel complementary field-effect transistors and methods of manufacture

Abstract: A transistor includes a gate dielectric overlying a channel region. A source region and a drain region are located on opposing sides of the channel region. The channel region is formed from a first semiconductor material and the source and drain regions are formed from a second semiconductor material. A gate electrode overlies the gate dielectric. A pair of spacers is formed on sidewalls of the gate electrode. Each of the spacers includes a void adjacent the channel region. A high-stress film can overlie the gate electrode and spacers.

A scaleable model for STI mechanical stress effect on layout dependence of MOS electrical characteristics

Abstract: This paper demonstrates a new compact and scaleable model of mechanical stress effects on MOS electrical performance, induced by shallow trench isolation (STI). This model has included the influence of STI stress not only on the mobility and saturation velocity, but also on the threshold voltage and other important second-order effects. Thus it could simulate the layout dependence of MOS performance with good accuracy and efficiency. We have verified this model with various device dimensions and layout styles of our advanced MOS technologies. And it shows the importance of this new model for circuit design in advanced CMOS generations.

Semiconductor-on-insulator SRAM configured using partially-depleted and fully-depleted transistors

Abstract: A static memory element includes a first inverter having an input coupled to a left bit node and an output coupled to a right bit node. A second inverter has an input coupled to the right bit node and an output coupled to the left right bit node. A first fully depleted semiconductor-on-insulator transistor has a drain coupled to the left bit node, and a second fully depleted semiconductor-on-insulator transistor has a drain coupled to the right bit node.

Multiple-gate transistors with improved gate control

Abstract: A method for fabricating a multiple-gate device including the steps of providing a substrate of a semi-conducting layer on an insulator stack which includes an insulator layer overlying an etch-stop layer; patterning a semi-conducting layer forming a semiconductor fin; etching the insulator layer at the base of the fin forming an undercut; depositing a gate dielectric layer overlying the fin; depositing an electrically conductive layer over the gate dielectric layer; etching the electrically conductive layer forming a gate straddling across the two sidewall surfaces and the top surface of the fin; and forming a source region and a drain region in the fin.

Strained channel on insulator device

Abstract: A semiconductor device 10 includes a substrate 12 (e.g., a silicon substrate) with an insulating layer 14 (e.g., an oxide such as silicon dioxide) disposed thereon. A first semiconducting material layer 16 (e.g., SiGe) is disposed on the insulating layer 14 and a second semiconducting material layer 18 (e.g., Si) is disposed on the first semiconducting material layer 16. The first and second semiconducting material layers 16 and 18 preferably have different lattice constants such that the first semiconducting material layer 16 is compressive and the second semiconducting material layer is tensile 18.

Method for dicing semiconductor wafers

Abstract: A method provides for dicing a wafer having a base material with a diamond structure The wafer first undergoes a polishing process, in which a predetermined portion of the wafer is polished away from its back side The wafer is then diced through at least one line along a direction at a predetermined offset angle from a natural cleavage direction of the diamond structure A wafer is produced with one or more dies formed thereon with at least one of its edges at an offset angle from a natural cleavage direction of a diamond structure of a base material forming the wafer At least one dicing line has one or more protection elements for protecting the dies from undesired cracking while the wafer is being diced along the dicing line

Semiconductor diode with reduced leakage

Abstract: A diode 100 is formed on a silicon-on-insulator substrate that includes a silicon layer overlying an insulator layer 142 . An active region is formed in the silicon layer and includes a p-doped region 108 and an n-doped region 106 separated by a body region 110 . A high permittivity gate dielectric 114 overlies the body region 110 and a gate electrode 112 overlies the gate dielectric 114 . As an example, the diode can be used for ESD protection.

Strain balanced structure with a tensile strained silicon channel and a compressive strained silicon-germanium channel for CMOS performance enhancement

Abstract: A method of fabricating a CMOS device wherein mobility enhancement of both the NMOS and PMOS elements is realized via strain induced band structure modification, has been developed. The NMOS element is formed featuring a silicon channel region under biaxial strain while the PMOS element is simultaneously formed featuring a SiGe channel region under biaxial compressive strain. A novel process sequence allowing formation of a thicker silicon layer overlying a SiGe layer, allows the NMOS channel region to exist in the silicon layer overlying a SiGe layer, allows the NMOS channel region to exist in the silicon layer which is under biaxial tensile strain enhancing electron mobility. The same novel process sequence results in the presence of a thinner silicon layer, overlying the same SiGe layer in the PMOS region, allowing the PMOS channel region to exist in the biaxial compressively strained SiGe layer, resulting in hole mobility enhancement.

Contacts to semiconductor fin devices

Abstract: A method for forming a contact to a semiconductor fin which can be carried out by first providing a semiconductor fin that has a top surface, two sidewall surfaces and at least one end surface; forming an etch stop layer overlying the fin; forming a passivation layer overlying the etch stop layer; forming a contact hole in the passivation layer exposing the etch stop layer; removing the etch stop layer in the contact hole; and filling the contact hole with an electrically conductive material.

Moore's law lives on [CMOS transistors]

Abstract: We discuss several device structures suitable for scaling CMOS devices well into the nano-CMOS era, perhaps down below 10 nm physical gate length. The ultra-thin body MOSFET device structure has many features in common with today's bulk MOSFET, which makes it easier for industry to introduce into manufacturing. On the other hand, the double-gate structure as represented by the FinFET appears to offer greater scalability down to 10 nm gate length or perhaps even below. While a number of significant challenges remain to be overcome, including device parasitics, interfaces, and threshold voltage control techniques, it appears that the continued evolution of CMOS integrated circuit technology into this regime will not be impeded by basic limitations of the underlying transistor technology. The implication of this is that "Moore's law" may continue for yet another 15-20 years before the ultimate device limits for CMOS are reached.

Effect of liner thickness on electromigration lifetime

Abstract: Electromigration lifetime was measured as a function of liner thickness for Cu/SiO2 interconnect structures. A significant increase in mean lifetime was observed for structures in which the liner thickness at the base of the test via was less than approximately 6 nm, with a current density <5 mA/μm2 in the power line connected to the test via. This is attributed to the continuous flow of Cu across the thin and possibly discontinuous liner at the base of the via. For extremely thin liner coverage, <1.4 nm at the base of the via and 2.5 at the bottom of the test line, the mean lifetime was observed to decrease as a rapid diffusion path was created which partially offset the beneficial effects of continuous flow. Failure distributions appeared to be trimodal and this was confirmed through failure analysis. In the case of thin liner coverage (<6 nm), early fails, which are typically characterized by slitlike voids at the via/line interface, were not observed.

Bonded soi wafer with device layer and substrate for performance improvement

Abstract: A new silicon structure is provided. Under a first embodiment of the invention, a first silicon substrate having a crystallographic orientation is bonded to the surface of a second silicon substrate having a crystallographic orientation, the wafer alignment notch of the first and the second silicon substrates are aligned with each other. Under a first embodiment of the invention, a first silicon substrate having a crystallographic orientation is bonded to the surface of a second silicon substrate having a crystallographic orientation, the wafer alignment notch of the first and the second silicon substrates are not aligned with each other.

Silicon strain engineering accomplished via use of specific shallow trench isolation fill materials

Abstract: A method of forming a strained silicon layer created via a material mis-match with adjacent trench isolation (TI), regions filled with a dielectric layer comprised with either a higher, or lower thermal expansion coefficient than that of silicon, has been developed. Filling of trenches with a dielectric layer comprised with a higher thermal expansion coefficient than that of silicon results in a tensile strain in planar direction and compressive strain in vertical direction, in an adjacent silicon region. Enhanced electron mobility in channel regions of an N channel MOSFET device, and enhanced hole mobility and transit time in an N type base region of a vertical PNP bipolar device, is realized when these elements are formed in the silicon layer under tensile strain. Filling of trenches with a dielectric layer comprised with a lower thermal expansion coefficient than the thermal expansion coefficient of silicon results in a compressive strain in planar directions and tensile strain in vertical directions, in an adjacent silicon region. Enhanced hole mobility in channel regions of an P channel MOSFET device, and enhanced electron mobility and transit time in a P type base region of a vertical NPN bipolar device, is realized when these elements are formed in the silicon layer under compressive strain.

Interconnect with composite barrier layers and method for fabricating the same

Abstract: Composite ALD-formed diffusion barrier layers. In a preferred embodiment, a composite conductive layer is composed of a diffusion barrier layer and/or a low-resistivity metal layer formed by atomic layer deposition (ALD) lining a damascene opening in dielectrics, serving as diffusion blocking and/or adhesion improvement. The preferred composite diffusion barrier layers are dual titanium nitride layers or dual tantalum nitride layers, triply laminar of tantalum, tantalum nitride and tantalum-rich nitride, or tantalum, tantalum nitride and tantalum, formed sequentially on the opening by way of ALD.

Loop-based interconnect modeling and optimization approach for multigigahertz clock network design

Abstract: A highly efficient loop-based interconnect modeling methodology is proposed for multigigahertz clock network design and optimization. Closed-form loop resistance and inductance models are proposed for fully shielded global clock interconnect structures, which capture high-frequency effects including inductance and proximity effects. The models are validated through comparisons with electromagnetic simulations and measured data taken from a Power4 chip. This modeling methodology greatly improves the clock interconnect simulation efficiency and enables fast physical design exploration. Examples of interconnect performance optimization are demonstrated and design guidelines are proposed.

On the body-source built-in potential lowering of SOI MOSFETs

Abstract: This letter provides a viewpoint for the characterization of state-of-the-art thin film silicon-on-insulator (SOI) MOSFETs. Based on body-source built-in potential lowering, the degree of full depletion can be quantified. In addition to serving as a measure of the floating-body behavior of SOI devices, the concept also enables the consolidation of partial-depletion (PD) and full-depletion (FD) SOI compact models. This consolidation of compact models together with the trend of coexistence of PD/FD devices in a single chip has become one of the greatest challenges in the scaling of SOI CMOS.

Strained silicon layer semiconductor product employing strained insulator layer

Abstract: A strained silicon layer fabrication and a method for fabrication thereof employ a strained insulator material layer formed over a strained silicon layer in turn formed upon a strained silicon-germanium alloy material layer which is formed upon a relaxed material substrate. The strained insulator material layer provides increased fabrication options which provide for enhanced fabrication efficiency when fabricating the strained silicon layer fabrication.

Strained silicon structure

Abstract: A semiconductor device includes a substrate, a first epitaxial layer, a second epitaxial layer, a third epitaxial layer, a first trench, and a second trench. The first epitaxial layer is formed on the substrate. The first layer has lattice mismatch relative to the substrate. The second epitaxial layer is formed on the first layer, and the second layer has lattice mismatch relative to the first layer. The third epitaxial layer is formed on the second layer, and the third layer has lattice mismatch relative to the second layer. Hence, the third layer may be strained silicon. The first trench extends through the first layer. The second trench extends through the third layer and at least partially through the second layer. At least part of the second trench is aligned with at least part of the first trench, and the second trench is at least partially filled with an insulating material.