Showing papers by "Chenming Hu published in 2004"

5nm-gate nanowire FinFET

Abstract: A new nanowire FinFET structure is developed for CMOS device scaling into the sub-10 nm regime. Accumulation mode P-FET and inversion mode N-FET with 5 nm and 10 nm physical gate length, respectively, are fabricated. N-FET gate delay (CV/I) of 0.22 ps and P-FET gate delay of 0.48 ps with excellent subthreshold characteristics are achieved, both with very low off leakage cur-rent less than 10 nA/ /spl mu/m. Nanowire FinFET device operation is also explored using 3-D full quantum mechanical simulation.

Immersion Fluid for Immersion Lithography, and Method of Performing Immersion Lithography

Abstract: An immersion lithographic system 10 comprises an optical surface 51, an immersion fluid 60 with a pH less than 7 contacting at least a portion of the optical surface, and a semiconductor structure 80 having a topmost photoresist layer 70 wherein a portion of the photoresist is in contact with the immersion fluid. Further, a method for illuminating a semiconductor structure 80 having a topmost photoresist layer 70 comprising the steps of: introducing an immersion fluid 60 into a space between an optical surface 51 and the photoresist layer wherein the immersion fluid has a pH of less than 7, and directing light preferably with a wavelength of less than 450 nm through the immersion fluid and onto the photoresist.

Lithography apparatus for manufacture of integrated circuits

Abstract: An immersion lithographic system 10 comprises an optical surface 51 , an immersion fluid 60 contacting at least a portion of the optical surface, and a semiconductor structure 80 having a topmost photoresist layer 70 having a thickness of less than about 5000 angstroms, wherein a portion of the photoresist is in contact with the immersion fluid. Further, a method for illuminating a semiconductor structure 80 having a topmost photoresist layer 70 with a thickness of less than about 5000 angstroms, comprising introducing an immersion fluid 60 into a space between an optical surface 51 and the photoresist layer, and directing light preferably with a wavelength of less than about 450 nm through the immersion fluid and onto the photoresist.

Characterization of spatial intrafield gate CD variability, its impact on circuit performance, and spatial mask-level correction

Abstract: The authors present a comprehensive characterization method applied to the study of the state-of-the-art 18-/spl mu/m CMOS process. Statistical characterization of gate CD reveals a large spatial intrafield component, strongly dependent on the local layout patterns. The authors describe the statistical analysis of this data and demonstrate the need for such comprehensive characterization. They describe the experimental setup of the novel measurement-based characterization approach that is capable of capturing all the relevant CD variation patterns necessary for accurate circuit modeling and statistical design for increased performance and yield. Characterization is based upon an inexpensive electrically based measurement technique. A rigorous statistical analysis of the impact of intrafield variability on circuit performance is undertaken. They show that intrafield CD variation has a significant detrimental effect on the overall circuit performance that may be as high as 25%. Moreover, they demonstrate that the spatial component of gate CD variability, rather than the proximity-dependent component, is predominantly responsible for speed degradation. In order to reduce the degradation of circuit performance and yield, the authors propose a mask-level spatial gate CD correction algorithm to reduce the intrafield and overall variability and provide an analytical model to evaluate the effectiveness of correction for variance reduction. They believe that potentially significant benefits can be achieved through implementation of this compensation technique in the production environment.

Dual work function CMOS gate technology based on metal interdiffusion

Abstract: A gate structure for a MOSFET device comprises a gate insulation layer, a first layer of a first metal abutting the gate insulation layer, and a second layer overlying the first layer and comprising a mixture of the metal of the first layer and a second metal, the metal layers formed by the diffusion of the first metal into and through the second metal. The second metal can be used as the gate for a n-MOS transistor, and the mixture of first metal and second metal overlying a layer of the first metal can be used as a gate for a p-MOS transistor where the first metal has a work function of about 5.2 eV and the second metal has a work function of about 4.1 eV.

Methods and structures for planar and multiple-gate transistors formed on SOI

Abstract: A semiconductor device includes an insulator layer, a semiconductor layer, a first transistor, and a second transistor. The semiconductor layer is overlying the insulator layer. A first portion of the semiconductor layer has a first thickness. A second portion of the semiconductor layer has a second thickness. The second thickness is larger than the first thickness. The first transistor has a first active region formed from the first portion of the semiconductor layer. The second transistor has a second active region formed from the second portion of the semiconductor layer. The first transistor may be a planar transistor and the second transistor may be a multiple-gate transistor, for example.

Device having multiple silicide types and a method for its fabrication

Abstract: Provided are a semiconductor device and a method for its fabrication. In one example, the semiconductor device includes an active region formed on a substrate using a first silicide type and another active region formed on the substrate using another silicide type. The two silicide types differ and at least one of the two silicides is an alloy silicide. An etch stop layer may overlay at least one of the silicide regions.

Effects of overlayers on electromigration reliability improvement for Cu/low K interconnects

Abstract: Electromigration in Cu Damascene lines capped with either a CoWP, Ta/TaN, SiN/sub x/, or SiC/sub x/N/sub y/H/sub z/ layer was reviewed. A thin CoWP or Ta/TaN cap on top of the Cu line surface significantly reduced interface diffusion and improved the electromigration lifetime when compared with lines capped with SiN/sub x/ or SiC/sub x/N/sub y/H/sub z/. Activation energies for electromigration were found to be 2.0 eV, 1.4 eV, and 0.85-1.1 eV for the Cu lines capped with CoWP, Ta/TaN, and SiN/sub x/ or SiC/sub x/N/sub y/H/sub z/, respectively.

CMOS logic gate fabricated on hybrid crystal orientations and method of forming thereof

Abstract: In preferred embodiments of the present invention, a method of forming CMOS devices using SOI and hybrid substrate orientations is described. In accordance with a preferred embodiment, a substrate may have multiple crystal orientations. One logic gate in the substrate may comprise at least one N-FET on one crystal orientation and at least one P-FET on another crystal orientation. Another logic gate in the substrate may comprise at least one N-FET and at least one P-FET on the same orientation. Alternative embodiments further include determining the preferred cleavage planes of the substrates and orienting the substrates relative to each other in view of their respective preferred cleavage planes. In a preferred embodiment, the cleavage planes are not parallel.

Device challenges and opportunities

Abstract: CMOS technology is facing exciting opportunities and formidable challenges. They include mobility scaling to overcome the speed/power barrier, new gate-stack materials and/or new device structures; to overcome the gate-length/leakage barrier; nonvolatile memory and universal memory to enlarge the market, and containment of costs. CMOS has much more to give in the next two decades, yet it is not too early, especially in universities, to start searching for not-CMOS-like circuit/system architectures that may require non-existing new devices but offer the promise of dramatic reduction in power and cost.

Ultra-shallow junction MOSFET having a high-k gate dielectric and in-situ doped selective epitaxy source/drain extensions and a method of making same

Abstract: A MOSFET includes a gate having a high-k gate dielectric on a substrate and a gate electrode on the gate dielectric. The gate dielectric protrudes beyond the gate electrode. A deep source and drain having shallow extensions are formed on either side of the gate. The deep source and drain are formed by selective in-situ doped epitaxy or by ion implantation and the extensions are formed by selective, in-situ doped epitaxy. The extensions lie beneath the gate in contact with the gate dielectric. The material of the gate dielectric and the amount of its protrusion beyond the gate electrode are selected so that epitaxial procedures and related procedures do not cause bridging between the gate electrode and the source/drain extensions. Methods of fabricating the MOSFET are described.

Gate electrode for a semiconductor fin device

Abstract: A method for forming a gate electrode for a multiple gate transistor provides a doped, planarized gate electrode material which may be patterned using conventional methods to produce a gate electrode that straddles the active area of the multiple gate transistor and has a constant transistor gate length. The method includes forming a layer of gate electrode material having a non-planar top surface, over a semiconductor fin. The method further includes planarizing and doping the gate electrode material, without doping the source/drain active areas, then patterning the gate electrode material. Planarization of the gate electrode material may take place prior to the introduction and activation of dopant impurities or it may follow the introduction arid activation of dopant impurities. After the gate electrode is patterned, dopant impurities are selectively introduced to the semiconductor fin to form source/drain regions.

Method of fabricating a necked FINFET device

Abstract: A method of fabricating a double gate, FINFET device structure in a silicon on insulator layer, in which the channel region formed in the SOI layer is defined with a narrowed, or necked shape, and wherein a composite insulator spacer is formed on the sides of the device structure, has been developed. A FINFET device structure shape is formed in an SOI layer via anisotropic RIE procedures, followed by a growth of a silicon dioxide gate insulator layer on the sides of the FINFET device structure shape. A gate structure is fabricated traversing the device structure and overlying the silicon dioxide gate insulator layer located on both sides of the narrowest portion of channel region. After formation of a source/drain region in wider, non-channel regions of the FINFET device structure shape, composite insulator spacers are formed on the sides of the FINFET shape and on the sides of the gate structure. Metal silicide is next formed on source/drain regions resulting in a FINFET device structure featuring a narrow channel region, and surrounded by composite insulator spacers located on the sides of the device structure.

Semiconductor device with high-k gate dielectric

Abstract: An integrated circuit includes a substrate, a first transistor, and a second transistor. The first transistor has a first gate dielectric portion located between a first gate electrode and the substrate. The first gate dielectric portion includes a first high-permittivity dielectric material and/or a second high-permittivity dielectric material. The first gate dielectric portion has a first equivalent silicon oxide thickness. The second transistor has a second gate dielectric portion located between a second gate electrode and the substrate. The second gate dielectric portion includes the first high-permittivity dielectric material and/or the second high-permittivity dielectric material. The second gate dielectric portion has a second equivalent silicon oxide thickness. The second equivalent silicon oxide thickness may be different than the first equivalent silicon oxide thickness.

Suppression of MOSFET gate leakage current

Abstract: A method for forming a MOSFET having greatly reduced leakage current between the gate electrode and the channel, source and drain regions. The method requires the use of gate electrode materials having lower electron affinities than the channel, source and drain regions. Gate electrode materials with negative electron affinities will also achieve the objectives of the invention. The use of these gate electrode materials enables the band structures of the gate electrode and the other regions to be aligned in a manner that eliminates tunneling states for carriers tunneling between the gate and the body of the device.

Complementary field-effect transistors and methods of manufacture

Abstract: A complementary FET and a method of manufacture is provided. The complementary FET utilizes a substrate having a surface layer with a crystal orientation. Tensile stress, which increases performance of the NMOS FETs, is added by silicided source/drain regions, tensile-stress film, shallow trench isolations, inter-layer dielectric, or the like.

Transistor with a strained region and method of manufacture

Abstract: A transistor structure comprises a channel region overlying a substrate region The substrate region comprises a first semiconductor material with a first lattice constant The channel region comprises a second semiconductor material with a second lattice constant The source and drain regions are oppositely adjacent the channel region and the top portion of the source and drain regions comprise the first semiconductor material A gate dielectric layer overlies the channel region and a gate electrode overlies the gate dielectric layer

Modeling the floating-body effects of fully depleted, partially depleted, and body-grounded SOI MOSFETs

Abstract: This paper describes a unified framework to model the floating-body effects of various SOI MOSFET operation modes, including body-contacted mode, partially depleted mode and fully depleted mode. As the operation mode is dimension and bias dependent, different modes can co-exist in a single SOI technology. A smooth transit from one type of operation mode to another is thus essential and has been included in the model. In addition, the floating-body effects can couple to a number of other SOI specific phenomena such as heating assisted impact ionization, gate tunneling induced dynamic behavior, and operation mode dependent small signal output resistance. A methodology to model the overall SOI MOSFET behavior due to the combination of multiple floating-body related effects will also be described.

Semiconductor-on-insulator chip with -oriented transistors

Abstract: A semiconductor-on-insulator device includes a silicon active layer with a crystal direction placed over an insulator layer. The insulator layer is placed onto a substrate with a crystal direction. Transistors oriented on a direction are formed on the silicon active layer.

Method of fabricating a wafer with strained channel layers for increased electron and hole mobility for improving device performance

Abstract: A method for making a SOI wafer with a strained silicon layer for increased electron and hole mobility is achieved. The method forms a porous silicon layer on a seed wafer. A H2 anneal is used to form a smooth surface on the porous silicon. A strain free (relaxed) epitaxial SixGe1-x layer is deposited and a bonding layer is formed. The seed wafer is then bonded to a handle wafer having an insulator on the surface. A spray etch is used to etch the porous Si layer resulting in a SOI handle wafer having portions of the porous Si layer on the relaxed SixGe1-x. The handle wafer is then annealed in H2 to convert the porous Si to a smooth strained Si layer on the relaxed SiGe layer of the SOI wafer.

A non-charge-sheet based analytical model of undoped symmetric double-gate MOSFETs using SPP approach

Abstract: A non-charge-sheet based analytical model of undoped symmetric double-gate MOSFETs is developed in this paper using the SPP (surface potential plus) approach. The essential difference of the present theory compared with the previous lies in that the Poisson equation is solved in the term of the electron concentration rather than the term of the surface potential. This solution formulates the electrical field surface potential in inversion charge terms rather than the surface potential. Thus, a non-charge-sheet-based analytical solution of inversion charge is obtained directly, replacing the solution of transcendent equation groups of the surface potential. The obtained inversion charge relation then serves to develop a non-charge-sheet-based analytical theory for undoped symmetric double-gate MOSFETs from the Pao-Sah current formulation. The formulated model has an analytic form that does not need to solve for the transcendent equation as in the conventional surface potentials or Pao-Sah formulation. The validity of the model has also been demonstrated by extensive comparison with AMD double-gate MOSFET data.

A non-charge-sheet analytic theory for undoped symmetric double-gate MOSFETs from the exact solution of Poisson's equation using SPP approach

Abstract: A non-charge-sheet based analytic theory for undoped symmetric double-gate MOSFETs is presented in this paper. The formulation is based on the exact solution of the Poisson’s equation to solve for electron concentration directly rather than relying on the surface potential alone. Therefore, carrier distribution in the channel away from the surface is also taken care, giving a non-charge-sheet model compatible with the classical Pao-Sah model. The formulated model has an analytic form that does not need to solve for the transcendent equation as in the conventional surface potentials or Pao-Sah formulation. The validity of the model has also been demonstrated by extensive comparison with AMD double-gate MOSFET’s data

Contacts to semiconductor fin device and method for manufacturing the same

Abstract: Contacts to a semiconductor fin device and a method for manufacturing the same are disclosed, and each of the contacts are located on a top surface, two sidewalls surfaces, and/or at last one end surface of a semiconductor fin, so that the contacts having a large contact area to a source/drain of the semiconductor fin device are obtained.

BSIM5 MOSFET Model

Abstract: This paper summarizes BSIM5 MOSFET model for aggressively scaled CMOS technology which was released recently. Various new physical effects are timely addressed in the new physical core including more accurate physics that is easily extended to non-charge-sheet, completely continuous current and derivatives, and extendibility to non-traditional CMOS based devices including SOI and double-gate MOSFETs. The flexible architecture also enables the carry-over of BSFM4's accurate modeling of numerous device behaviors attributable to device physics or technologies.

Low power device technology with SiGe channel, HfSiON, and poly-Si gate

Abstract: We report solutions to the formidable challenges posed by integrating a HfSiON dielectric with a poly-Si gate for low-power device technology. A 1.5 nm EOT HfSiON is demonstrated with mobility comparable to SiO/sub 2/ and 3 orders of magnitude leakage reduction. A novel boron delta-doped strained-SiGe channel points a way out of the high threshold voltage problem associated with Fermi-pinning at the high-k/poly-Si interface and ameliorates short-channel effects in PMOS devices. In addition, a 20% hole mobility enhancement and 15% I/sub on/-I/sub off/ characteristics improvement are achieved owing to the compressive SiGe channel. NMOS PBTI lifetime of 35 years, and PMOS NBTI and NMOS hot carrier lifetimes of more than 1000 years are demonstrated at 1.2 V.

Method for forming devices with multiple spacer widths

Abstract: A method is described for forming three or more spacer widths in transistor regions on a substrate. In one embodiment, different silicon nitride thicknesses are formed above gate electrodes followed by nitride etching to form spacers. Optionally, different gate electrode thicknesses may be fabricated and a conformal oxide layer is deposited which is subsequently etched to form different oxide spacer widths. A third embodiment involves a combination of different gate electrode thickness and different nitride thicknesses. A fourth embodiment involves selectively thinning an oxide layer over certain gate electrodes before etching to form spacers. Therefore, spacer widths can be independently optimized for different transistor regions on a substrate to enable better drive current in transistors with narrow spacers and improved SCE control in neighboring transistors with wider spacers. Better drive current is also obtained in transistors with shorter polysilicon thickness.

Silicide/semiconductor structure and method of fabrication

Abstract: A preferred embodiment of the present invention comprises a dielectric/metal/2 nd energy bandgap (E g ) semiconductor/1 st E g substrate structure. In order to reduce the contact resistance, a semiconductor with a lower energy bandgap (2 nd E g ) is put in contact with metal. The energy bandgap of the 2 nd E g semiconductor is lower than the energy bandgap of the 1 st E g semiconductor and preferably lower than 1.1 eV. In addition, a layer of dielectric may be deposited on the metal. The dielectric layer has built-in stress to compensate for the stress in the metal, 2 nd E g semiconductor and 1 st E g substrate. A process of making the structure is also disclosed.

Successful dual damascene integration of extreme low k materials (k < 2.0) using a novel gap fill based integration scheme

Abstract: In this communication, a novel scheme known as the etch back/gapfill (EBGF) integration scheme was introduced and shown to overcome most of the well known challenges (2) that are expected to complicate the integration of porous low k materials. It was shown that this integration scheme can be used to successfully generate multi-level dual damascene structures using intermetal dielectric (IMD) materials with k less than 2.0 with promising yield and reliability. It has been demonstrated that EBGF integration is a promising method to integrate fragile porous low k materials into BEOL structures by avoiding most of the major processing issues associated with such materials. By using this scheme, new ultra-low k and extreme low k materials can be introduced with limited modification to the existing dense IMD fabrication infrastructure while increasing the performance of the interconnects substantially. As such the method offers a potential to break through what is now commonly referred to as the "red brick wall" in the BEOL part of the ITRS roadmap.

Improved Cobalt Silicidation Process for Substrates with a Silicon Germanium Layer

Abstract: A method comprises providing a semiconductor alloy layer on a semiconductor substrate, forming a gate structure on the semiconductor alloy layer, forming source and drain regions in the semiconductor substrate on both sides of the gate structure, removing at least a portion of the semiconductor alloy layer overlying the source and drain regions, and forming a metal silicide region over the source and drain regions.