Showing papers by "Chenming Hu published in 2006"

Germanium-source tunnel field effect transistors with record high I ON /I OFF

Abstract: Tunnel field effect transistors (TFETs) with record high I ON /I OFF ratio (≫106) for low-voltage (0.5V) operation are achieved by using germanium in the source region to achieve a small tunnel bandgap. The measured data are well explained by the theoretical band-to-band tunneling current model. Using the calibrated analytical model, the energy-delay performance of TFET-based technology is compared against that of conventional CMOS technology, at the 65nm node. The TFET is projected to provide dramatic improvement in energy efficiency for performance in the range up to ∼0.5GHz.

Apparatus and method for manufacturing a semiconductor wafer with reduced delamination and peeling

Abstract: A multi-layered semiconductor structure with free areas limiting the placement of test keys. First and second scribe lines intersect to define one corner point of a die. The first and second scribe lines are part of the multilayered structure and at least one layer of the multi-layer structure is a low-k dielectric layer. Free area A1 is defined on the first scribe line and is defined by the equation A1=D1×S1, where D1 is the distance from the corner point of the die toward the main area of the die, and S1 is the width of the first scribe line. Free area AS is defined at the intersection of the first scribe line and the second scribe line adjacent the die and is defined by the equation AS=S1×S2, where S2 is the width of the second scribe line.

Doping of semiconductor fin devices

Abstract: A semiconductor structure includes of a plurality of semiconductor fins overlying an insulator layer, a gate dielectric overlying a portion of said semiconductor fin, and a gate electrode overlying the gate dielectric. Each of the semiconductor fins has a top surface, a first sidewall surface, and a second sidewall surface. Dopant ions are implanted at a first angle (e.g., greater than about 7°) with respect to the normal of the top surface of the semiconductor fin to dope the first sidewall surface and the top surface. Further dopant ions are implanted with respect to the normal of the top surface of the semiconductor fin to dope the second sidewall surface and the top surface.

Modeling Advanced FET Technology in a Compact Model

Abstract: The need for meeting the expectations of continuing the enhancement of CMOS performance and density has inspired the introduction of new materials into the classical single-gate bulk MOSFET and the development of nonclassical multigate transistors at an accelerated rate. There is a strong need to understand and model the associated new physics and electrical behavior to ensure widespread very-large-scale-integration circuit applications of new technologies. This paper presents some of the efforts toward the modeling of new technologies for bulk MOSFETs and multigate transistors. A holistic model for mobility enhancement through process-induced stress and a dynamic behavior model for high-k transistors have been developed to capture some of the new effects and new materials in the bulk MOSFET. A new analytical model is also presented for the fundamentally new device structure-FinFET

Strained channel complementary field-effect transistors

Abstract: A transistor includes a gate dielectric overlying a channel region. A source region and a drain region are located on opposing sides of the channel region. The channel region is formed from a first semiconductor material and the source and drain regions are formed from a second semiconductor material. A gate electrode overlies the gate dielectric. A pair of spacers is formed on sidewalls of the gate electrode. Each of the spacers includes a void adjacent the channel region. A high-stress film can overlie the gate electrode and spacers.

MOSFET design for forward body biasing scheme

Abstract: Forward body biasing is a solution for continued scaling of bulk-Si CMOS technology. In this letter, the dependence of 30-nm-gate MOSFET performance on body bias is experimentally evaluated for devices with various channel-doping profiles to provide guidance for channel engineering in a forward body-biasing scheme. Furthermore, simulations of 10-nm-gate CMOS (hp22-nm node) devices are performed to study the optimal channel-doping profile and gate work function engineering for a forward biasing scheme.

Programming characteristics of the steep turn-on/off feedback FET (FBFET)

Abstract: The feedback FET is a new steep turn-on/off transistor which achieves six-orders-of-magnitude current change within a 2 mV gate voltage step (0.35 mV/decade). This device requires an initial programming or conditioning step. Its threshold voltage may be adjusted by Fowler-Nordheim or hot-carrier charge injection. Programming and operation of the device is explained with simulation and experimental data.

Capacitor that includes high permittivity capacitor dielectric

Abstract: A decoupling capacitor is formed on a semiconductor substrate that includes a silicon surface layer. A substantially flat bottom electrode is formed in a portion of the semiconductor surface layer. A capacitor dielectric overlies the bottom electrode. The capacitor dielectric is formed from a high permittivity dielectric with a relative permittivity, preferably greater than about 5. The capacitor also includes a substantially flat top electrode that overlies the capacitor dielectric. In the preferred application, the top electrode is connected to a first reference voltage line and the bottom electrode is connected to a second reference voltage line.

MOSFET hot-carrier reliability improvement by forward-body bias

Abstract: Active threshold voltage V/sub TH/ control via well-substrate biasing can be utilized to satisfy International Roadmap for Semiconductors performance and standby power requirements for CMOS technology beyond the hp65-nm node. In this letter, the impact of substrate bias V/sub SUB/ on hot-carrier reliability is presented. The impact varies with the gate length and body effect factor. These findings are explained, and the effects of future scaling are discussed using a quasi-two-dimensional model. Significant and important improvement in hot-carrier lifetime with forward-bias V/sub SUB/ can be expected for deeply scaled CMOS devices, making it an attractive method for extending the scalability of bulk-Si transistor technology.

Physical, Electrical, and Reliability Characterization of Ru for Cu Interconnects

Abstract: Thin film characterization, electrical performance, and preliminary reliability of physical vapor-deposited (PVD) TaN/chemical vapor-deposited (CVD) Ru bilayer were carried out to evaluate its feasibility as a liner layer for back-end of line (BEOL) Cu-low k integration. Adhesion and barrier strength were studied using 4-point bend, X-ray diffraction (XRD), and triangular voltage sweep (TVS) techniques. Electrical yields and line/via resistances were measured at both single and dual damascene levels, with PVD TaN/Ta liner layer as a baseline control. Reliability studies included electromigration (EM) and current-voltage (I-V) breakdown tests

Method for forming a device having multiple silicide types

Abstract: Provided is a semiconductor device and a method for its fabrication. The device includes a semiconductor substrate, a first silicide in a first region of the substrate, and a second silicide in a second region of the substrate. The first silicide may differ from the second silicide. The first silicide and the second silicide may be an alloy silicide.

Novel dual-metal gate technology using Mo-MoSi/sub x/ combination

Abstract: A novel dual-metal gate technology that uses a combination of Mo-MoSi/sub x/ gate electrodes is proposed. An amorphous-Si/Mo stack was fabricated as a gate electrode for the n-channel device. It was thermally annealed to form MoSi/sub x/. Pure Mo served as the gate electrode for the p-channel device. The work functions of MoSi/sub x/ and pure Mo gates on SiO/sub 2/ are 4.38 and 4.94 eV, respectively, which are appropriate for devices with advanced transistor structures. The small increase in the work function (< 20 meV) and the negligible equivalent oxide thickness variation (< 0.08 nm) after rapid thermal annealing at 950 /spl deg/C for 30 s also demonstrate the excellent thermal stabilities of Mo and MoSi/sub x/ on SiO/sub 2/. Additional arsenic ion implantation prior to silicidation was demonstrated further to lower the work function of MoSi/sub x/ to 4.07 eV. This approach for modulating the work function makes the proposed combination of Mo-MoSi/sub x/ gate electrodes appropriate for conventional bulk devices. The developed dual-metal-gate technology on HfO/sub 2/ gate dielectric was also evaluated. The effective work functions of pure Mo and undoped MoSi/sub x/ gates on HfO/sub 2/ are 4.89 and 4.34 eV, respectively. A considerable work-function shift was observed on the high-/spl kappa/ gate dielectric. The effect of arsenic preimplantation upon the work function of the metal silicide on HfO/sub 2/ was also demonstrated, even though the range of modulation was a little reduced.

Effect of Fluorine Incorporation on 1/f Noise of HfSiON FETs for Future Mixed-Signal CMOS

Abstract: An effect of fluorine incorporation into HfSiON on 1/f noise is shown for the first time. Fluorine effect on 1/f noise for SiON and HfSiON devices differ in that F does not improve the HfSiON N-FET 1/f noise. Apparently, the interface traps created by Hf close to the conduction band cannot be passivated by fluorine. For future analog/mixed -signal applications, HfSiON P-FET is expected to limit noise performance even though F can improve its noise

Necked Finfet device

Abstract: A method of fabricating a double gate, FINFET device structure in a silicon on insulator layer, in which the channel region formed in the SOI layer is defined with a narrowed, or necked shape, and wherein a composite insulator spacer is formed on the sides of the device structure, has been developed. A FINFET device structure shape is formed in an SOI layer via anisotropic RIE procedures, followed by a growth of a silicon dioxide gate insulator layer on the sides of the FINFET device structure shape. A gate structure is fabricated traversing the device structure and overlying the silicon dioxide gate insulator layer located on both sides of the narrowest portion of channel region. After formation of a source/drain region in wider, non-channel regions of the FINFET device structure shape, composite insulator spacers are formed on the sides of the FINFET shape and on the sides of the gate structure. Metal silicide is next formed on source/drain regions resulting in a FINFET device structure featuring a narrow channel region, and surrounded by composite insulator spacers located on the sides of the device structure.

Methods of forming semiconductor devices with high-k gate dielectric

Abstract: A method of fabricating an integrated circuit is provided. A first gate dielectric portion is formed on a substrate in a first transistor region. The first gate dielectric portion includes a first high-permittivity dielectric material. The first gate dielectric portion has a first equivalent silicon oxide thickness. A second gate dielectric portion is formed on the substrate in a second transistor region. The second gate dielectric portion includes the first high-permittivity dielectric material. The second gate dielectric portion has a second equivalent silicon oxide thickness. The second equivalent silicon oxide thickness is different than the first equivalent silicon oxide thickness.

Impact of HfSiON Induced Flicker Noise on Scaling of Future Mixed-Signal CMOS

Abstract: It is shown for the first time that HfSiON gate dielectric thickness has a strong impact on the flicker (1/f) noise of devices with Lg < 1mum. We have developed a simple model for both gate length (Lg) and HfSiON thickness dependences of N-FET flicker noise, based on excess traps at the gate-edges. P-FET noise does not exhibit such strong dependences. Scaling of future analog devices with high-k gate stack may be limited by noise considerations

BSIM4 and BSIM Multi-Gate Progress

Abstract: New technologies and alternate transistor structures are being developed to extend the CMOS scaling. Device models need to be developed and improved in parallel with the technology advancements to enable an efficient and quick adoption of the new technologies. Some of the recent advances in BSIM4 and BSIM Multi-gate models towards meeting this goal are presented in this paper. Improvements to the BSIM4 model include holistic stress-induced mobility enhancement model and a high-k dynamic behavior model. Preliminary results of the modeling of multi-gate architectures are also presented.

A Compact Quantum-Mechanical Model for Double-Gate MOSFET

Abstract: A bias-dependent QM correction for surface potential calculation is derived for DG MOSFETs. The QM-corrected surface potential agrees with the 2D simulation results well. This indicates that both Vth shift in the subthreshold and strong inversion regions and gate capacitance degradation in the strong inversion region due to QM are predicted simultaneously. The model can predict the complicated QM effect dependence on various device parameters, such as Nbody, Tsi, Tox, etc

On gate leakage current partition for MOSFET compact model

Abstract: Aggressive scaling of the gate-oxide thickness has made gate-tunneling current an essential aspect of MOSFET modeling and this leakage current density continues to increase for every process generation. Accurate compact models for gate-tunneling current and its source/drain partition are extremely critical to valid circuit performance in the 90 nm technology or beyond. Gate current partition has been studied by several authors [Cao K, et al. “BSIM4 gate leakage model including source–drain partition,” in IEDM Tech. Dig., San Francisco, CA, Dec. 2000. p. 815–8; R. van Langevelde et al., Gate current: modeling, ΔL extraction and impact on RF performance, in IEDM Tech. Dig., Washington, DC, Dec. 2001. p. 289–92; Shih W-K, et al., “A general partition scheme for gate leakage current suitable for MOSFET compact models,” in IEDM Tech. Dig., Washington DC., Dec. 2001. p. 293–6]. In this paper, an insight on the common/difference of these different gate leakage current partition schemes into source/drain has been provided and the accuracy of BSIM4 [Cao K, et al. “BSIM4 gate leakage model including source–drain partition,” in IEDM Tech. Dig., San Francisco, CA, Dec. 2000. p. 815–8] partition scheme is confirmed with comparing to the new derived equation, which incorporates the gate current into the inhomogeneous term calculation.

Alluminum base conductor for via fill interconnect

Abstract: A semiconductor device including a dielectric layer having a opening form therein having a cross-sectional area of less than 1 μm 2 and a PVD aluminum base conductor filled in the opening.

Dynamic Behavior Model for High-k MOSFETs

Abstract: The use of high -k dielectrics introduces new dynamic behavior into the transistor operation. In this work, an analytical model is derived to capture the dynamic behavior of a high-k transistor through the modeling of fast transient charging effects. WKB theory is used to determine the rate of ch arging/discharging of the traps. The model is verified against experimental data from literature. A sub -circuit adaptation of the model is developed to implement it in a general compact model framework. The sub-circuit is solved alongside the core transistor to capture the dynamic behavior of the transistor.

Semiconductor device, semiconductor chip, and method for manufacturing the semiconductor device

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor-on-insulator device comprising a transistor oriented in the orientation. SOLUTION: The semiconductor-on-insulator device includes silicon active layers 30a to 30d with a crystal orientation located on an insulating layer 40. The insulating layer 40 is located on a substrate 10 with crystal orientation. On the silicon active layers 30a to 30c, transistors 16 and 18 set in the direction are formed. COPYRIGHT: (C)2006,JPO&NCIPI

Aluminum based conductor for via fill and interconnect

Abstract: A semiconductor device including a dielectric layer having a opening form therein having a cross-sectional area of less than 1 μm 2 and a PVD aluminum base conductor filled in the opening.