Showing papers by "Chenming Hu published in 2009"

Modern Semiconductor Devices for Integrated Circuits

Abstract: 3. Electrons and holes are the major characters in the play and carry opposite charge. Their mass however is altered from the mass of an electron in vacuum. The altered mass is called e ective mass, mn and mp 4. The band model is the tool required for quantitative analysis of semiconductors. From this model one can get the energy gap, E-K diagrams allowing the determination of e ective masses, analysis of the energy levels with in the gap and the conduction/valence bands etc

Tunneling transistor suitable for low voltage operation

Abstract: Several embodiments of a tunneling transistor are disclosed. In one embodiment, a tunneling transistor includes a semiconductor substrate, a source region formed in the semiconductor substrate, a drain region formed in the semiconductor substrate, a gate stack including a metallic gate electrode and a gate dielectric, and a tunneling junction that is substantially parallel to an interface between the metallic gate electrode and the gate dielectric. As a result of the tunneling junction that is substantially parallel with the interface between the metallic gate electrode and the gate dielectric, an on-current of the tunneling transistor is substantially improved as compared to that of a conventional tunneling transistor. In another embodiment, a tunneling transistor includes a heterostructure that reduces a turn-on voltage of the tunneling transistor.

A Low Voltage Steep Turn-Off Tunnel Transistor Design

Abstract: —A new tunneling transistor structure is introduced that offers several advantages over prior designs. Notably, tunneling area is substantially increased. Turn on/off swing is improved by engineering doping profile to ensure tunneling initiates in high electric field region. TCAD simulations explore the critical design considerations. The concept of heterojunction tunneling is introduced as a means to achieve low effective band gap and low voltage operation for the design in consideration. I. I NTRODUCTION Increasing power consumption presents a major problem for future ICs. A transistor that can operate below 0.5 V supply is highly desirable. Maintaining large I on /I off ratio at such low V dd is a challenge for MOSFET given the 60 mV/decade subthreshold swing limit. This limit governs the turn off/on of any device based on flow of carriers over an energy barrier. Band-to-band tunneling (BTBT) is one process not subject to this limitation. Researchers have long explored the BTBT transistor [1-2]. However, all have relied on the same basic structure -- the gated PN diode. This conventional structure for an n-type FET is shown in Fig. 1. The location of tunneling is indicated by the arrow at the edge of the source region. The transistor “turns on” when the gate voltage exceeds the overlap voltage, V

Performance-Aware Corner Model for Design for Manufacturing

Abstract: We present a methodology to generate performance-aware corner models (PAMs). Accuracy is improved by emphasizing electrical variation data and reconciling the process and electrical variation data. PAM supports corner (plusmnsigma and plusmn 2sigma) simulation and Monte Carlo simulation. Furthermore, PAM supports the practice of application-specific corner cards, for example, for gain-sensitive applications.

Design of FinFET SRAM Cells Using a Statistical Compact Model

Abstract: A study of designing FinFET-based SRAM cells using a compact model is reported. Parameters for a multi-gate FET compact model, BSIM-MG are extracted from fabricated n-type and p-type SOI FinFETs. Local mismatch in gate length and fin width is calibrated to electrical measurements of 378 FinFET SRAM cells. The cell design is re-optimized through Monte Carlo statistical simulations. Variation in readability, writability and static leakage of the cell are studied.

Compact modeling of flicker noise variability in small size MOSFETs

Abstract: A compact model has been developed to capture the variability of flicker noise resulting from the reduction in size of state of the art MOSFETs The underlying physics of flicker noise in small area MOSFETs has been verified by two means: Monte Carlo simulation and analytic modeling The statistical distribution of flicker noise is reported for the first time, supported by experimental data from two sets of devices with different areas The developed model is capable of predicting the area dependence of noise at any frequency at desired %Yield

Three-dimensional measurement of line edge roughness in copper wires using electron tomography.

Abstract: Electrical interconnects in integrated circuits have shrunk to sizes in the range of 20-100 nm. Accurate measurements of the dimensions of these nanowires are essential for identifying the dominant electron scattering mechanisms affecting wire resistivity as they continue to shrink. We report a systematic study of the effect of line edge roughness on the apparent cross-sectional area of 90 nm Cu wires with a TaN/Ta barrier measured by conventional two-dimensional projection imaging and three-dimensional electron tomography. Discrepancies in area measurements due to the overlap of defects along the wire's length lead to a 5% difference in the resistivities predicted by the two methods. Tomography of thick cross sections is shown to give a more accurate representation of the original structure and allows more efficient sampling of the wire's cross-sectional area. The effect of roughness on measurements from projection images is minimized for cross-section thicknesses less than 50 nm, or approximately half the spatial frequency of the roughness variations along the length of the investigated wires.

Air-Spacer MOSFET With Self-Aligned Contact for Future Dense Memories

Abstract: An air-spacer transistor with self-aligned contact (SAC) is proposed. Air-spacer is created by removing the nitride spacer after the SAC plug has been formed. A three-dimensional mixed-mode simulation shows that this transistor structure has 35% smaller area, 10% faster speed, and 18% lower switching energy than a non-SAC MOSFET.

Electromigration Challenges for Nanoscale Cu Wiring

Abstract: Electromigration data and a theoretical model have shown that Cu lifetime in on‐chip Damascene interconnect structures has dropped for every new interconnect generation, even when tested at the same current density In addition, a mixture of bamboo and polycrystalline grain structures instead of a bamboo‐like structure observed for <90 nm wide lines (65 nm technology node) resulted in further lifetime degradation by the addition of grain boundary diffusion The techniques for improving EM lifetime either by modifying the interconnect structure by adding dummy vias on top of a Cu line, a Ru cap on the Cu top surface, or the formation of a thin CuSiN layer at the Cu/dielectric interface were investigated The upper dummy vias, the Ru cap or CuSiN layer on the top surface of the Cu lines interrupted the Cu mass flow along the top surface interface which can improve lifetimes The upper level dummy via structure was a powerful tool for helping to understand the Cu microstructure and to distinguish fast diffus

16nm functional 0.039µm 2 6T-SRAM cell with nano injection lithography, nanowire channel, and full TiN gate

Abstract: Record area size of 0.039µm2 for a functional 6T-SRAM cell has been successfully achieved with a novel Nano Injection Lithography (NIL) technique and dynamic Vdd regulator (DVR). The NIL technique is not only maskless for minimizing entry cost but also photoresist free to greatly enhance pattern resolution, down to 2nm 3-sigma line width roughness, and without significant proximity effect. Devices with nanowire channels and full TiN single gate for both N- and P-MOS are demonstrated with short channel and simplified integration process. This work discloses a new way to explore 16nm CMOS device and circuit design, and obtains early access to extreme CMOS scaling.

A comprehensive study of Ge 1−x Si x on Ge for the Ge nMOSFETs with tensile stress, shallow junctions and reduced leakage

Abstract: For the first time, growth of high-quality Ge-rich Ge 1−x Si x (0≤x≤0.14) layers on Ge substrate was demonstrated. An effective suppression of the phosphorus diffusion in Ge 1−x Si x and a better thermal stability of the nickel germanide on Ge 1−x Si x were observed. A higher rectifying ratio with a reduced diode leakage current in n+-Ge 1−x Si x /p-Ge 1−x Si x is compared with n+-Ge/p-Ge. These results indicate that it is suitable for Ge 1−x Si x to be used as source/drain (S/D) to fabricate the uniaxial tensile-strained channel Ge nMOSFETs.

Integration and reliability of CVD Ru cap for Cu/Low-k development

Abstract: Selective CVD Ru cap deposition process has been developed for BEOL Cu/Low-k integration. Selectivity of CVD Ru deposition between Cu and dielectrics is investigated. Electrical performance, electromigration (EM) lifetime, voltage ramp (I–V), and time -dependent-dielectric-breakdown (TDDB) are also characterized for Cu interconnects capped with CVD Ru. This selective CVD Ru cap process is a good candidate for 22nm and beyond technology nodes.

Reduce IC power consumption by >10x with a green transistor?

Abstract: Growing IC power use poses challenges for thermal management and electricity conservation. A low voltage green transistor could be the key to allowing more growth of microelectronics [1].

Gate last MOSFET with air spacer and self-aligned contacts for dense memories

Abstract: Gate-last metal-gate/high-k technology will allow MOSFET scaling to unprecedented levels. When the gate length is small, the dominant capacitance in the MOSFET is the gate to contact-plug capacitance. This is especially so with SAC (self-aligned contact) technology popular with high density memories. This papers proposes a compact SAC gate-last air-spacer structure that yield small size, high speed, and low switching energy. The improvement over the conventional SAC device increases dramatically with scaling.

Vacuum-sheath interconnect structure for dense memory

Abstract: A novel mostly-air interconnect structure is proposed. Every metal line is surrounded by an air vacuum sheath on all sides and supported on the bottom by a series of solid dielectric beams. The vias are also surrounded by vacuum sheaths. Computer simulation shows that the total capacitance of the interconnect is reduced by about 45% and the RC delay is decreased about 55%. The effective dielectric constant can be reduced to about 1.7 using existing dielectric with k=2.9.

Characterization of quantum-well and super-lattice lasers

Abstract: In this paper, we made an in-depth study on the fabrication of low-pressure MOCVD-grown 1055-1064 nm multi-quantum-well and super-lattice laser diodes, which can be used for green-light generation combined with second-harmonic generation crystal. Due to the simplicity of the configuration and high reliability, large merits in terms of size, cost, and power consumption would arise. Furthermore, direct modulation is possible in the laser diodes, which would lead to a highly compact pulsed laser source.

An in-depth study on the fabrication of 1055–1064 nm multi-quantum-well and super-lattice laser diodes

Abstract: The InGaAs/GaAs multi-quantum-well as well as the AlGaAs/GaAs and the GaAsP/GaAs super-lattice laser diodes were successfully fabricated by low-pressure MOCVD system, and a number of novel structures were explored in this systematic investigation. The strain-relief effect and the composition of cladding layers were analyzed in detail. Via a series of growth experiments, we concluded that better lasing efficiency and the minimum threshold current could be obtained from the sample made up of the AlGaAs/GaAs structure combined with the 60% Aluminum content of the AlGaAs cladding layer.