Showing papers by "Chenming Hu published in 2012"
TL;DR: In this article, the authors present the optimization of multiple-fin-height FinFET static random access memory (SRAM) to reduce cell leakage and improve the stability and density of SRAM.
Abstract: We present the optimization of multiple-fin-height FinFET static random access memory (SRAM) to reduce cell leakage and improve the stability and density of SRAM. Using a taller fin FinFET for the pull-down device increases the read static noise margin of the SRAM and can potentially reduce the SRAM cell area. A reasonable amount of channel doping in all the transistors can be used to reduce the cell leakage current without appreciably degrading the stability of the SRAM cell. Increasing the channel doping of the access transistor simultaneously improves the read stability and decreases the cell leakage current of the SRAM cell.
48 citations
TL;DR: In this article, the effects of impurities, Mn or Al, on interface and grain boundary electromigration (EM) in Cu damascene lines were investigated and it was found that the presence of bamboo grains in bamboo-polycrystalline lines played a critical role in slowing down the EM-induced void growth rate.
Abstract: The effects of impurities, Mn or Al, on interface and grain boundary electromigration (EM) in Cu damascene lines were investigated. The addition of Mn or Al solute caused a reduction in diffusivity at the Cu/dielectric cap interface and the EM activation energies for both Cu-alloys were found to increase by about 0.2 eV as compared to pure Cu. Mn mitigated and Al enhanced Cu grain boundary diffusion; however, no significant mitigation in Cu grain boundary diffusion was observed in low Mn concentration samples. The activation energies for Cu grain boundary diffusion were found to be 0.74 ± 0.05 eV and 0.77 ± 0.05 eV for 1.5 μm wide polycrystalline lines with pure Cu and Cu (0.5 at. % Mn) seeds, respectively. The effective charge number in Cu grain boundaries Z*GB was estimated from drift velocity and was found to be about −0.4. A significant enhancement in EM lifetimes for Cu(Al) or low Mn concentration bamboo-polycrystalline and near-bamboo grain structures was observed but not for polycrystalline-only alloy lines. These results indicated that the existence of bamboo grains in bamboo-polycrystalline lines played a critical role in slowing down the EM-induced void growth rate. The bamboo grains act as Cu diffusion blocking boundaries for grain boundary mass flow, thus generating a mechanical stress-induced back flow counterbalancing the EM force, which is the equality known as the “Blech short length effect.”
45 citations
12 Nov 2012
TL;DR: The BSIM-CMG model has been developed to model common symmetric double, triple, quadruple and surround gate MOSFETs as discussed by the authors, which is the surface potential based model for multi-gate MOSFs.
Abstract: BSIM compact models have served industry for more than a decade starting with BSIM3 and later BSIM4 and BSIMSOI. Here we will briefly discuss the ongoing work on current and future device models in BSIM group. BSIM6 is the next generation bulk RF MOSFET Model which uses charge based core with physical models adapted from BSIM4. Model fulfills all symmetry tests and shows correct slopes for harmonics. The BSIM-CMG and BSIM-IMG are the surface potential based models for multi-gate MOSFETs. The BSIM-CMG model has been developed to model common symmetric double, triple, quadruple and surround gate MOSFET. The BSIM-IMG model has been developed to model independent double-gate MOSFET capturing threshold voltage variation with back gate bias. Models include all read device effects like SCE, DIBL, mobility degradation, poly depletion, QME etc.
44 citations
TL;DR: In this article, a thermal network extraction methodology to characterize self-heating effect using two-port RF measurements is presented, and the technique of determining isothermal condition using only the selfheating (thermal) dominated range of the spectrum.
Abstract: In this letter, we present a thermal network extraction methodology to characterize self-heating effect using two-port RF measurements. We show the technique of determining isothermal condition using only the self-heating (thermal) dominated range of the spectrum. We use a self-consistent self-heating extraction scheme using both the real and imaginary parts of drain port admittance parameters. Appropriate thermal network is investigated, and a large amount of temperature rise due to self-heating is confirmed for short channel silicon-on-insulator MOSFETs with ultrathin body and buried oxide.
42 citations
TL;DR: In this article, a metal-gate Si-QD nonvolatile memory (NVM) with program/erase speed of 1μs under low operating voltages of ± 7
Abstract: The ultrafast metal-gate silicon quantum-dot (Si-QD) nonvolatile memory (NVM) with program/erase speed of 1 μs under low operating voltages of ± 7 V is achieved by thin tunneling oxide, in situ Si-QD-embedded dielectrics, and metal gate. Selective source/drain activation by green nanosecond laser spike annealing, due to metal-gate as light-blocking layer, responds to low thermal damage on gate structures and, therefore, suppresses re-crystallization/deformation/diffusion of embedded Si-QDs. Accordingly, it greatly sustains efficient charge trapping/de-trapping in numerous deep charge-trapping sites in discrete Si-QDs. Such a gate nanostructure also ensures excellent endurance and retention in the microsecond-operation Si-QD NVM.
42 citations
TL;DR: A turnkey, production circuit simulation ready compact model for cylindrical/surround gate transistors has been developed in this article, which contains an enhanced surface potential based description of the charge in the channel.
Abstract: A turnkey, production circuit simulation ready compact model for cylindrical/surround gate transistors has been developed. The core of the model contains an enhanced surface potential based description of the charge in the channel. Analytical expressions for channel current and terminal charges have been derived. A method to account for quantum confinement in the cylindrical structure in a compact model framework is described. For the first time we present calibration results of such a model to a cylindrical gate technology that also exhibits asymmetric I–V characteristics.
28 citations
23 Apr 2012
TL;DR: In this paper, the authors proposed a scaling path to scale the body thickness in proportion to gate length, which is similar to the scaling path of FinFETs for near-threshold circuits.
Abstract: FinFET provides needed relief to ICs from performance, power, and device variation predicaments. It also provides higher carrier mobility, especially at low voltage near the threshold voltage, giving promise to practical near-threshold circuits. Another new transistor conceived simultaneously with FinFET, UTB-SOI FET, is also entering production. Together they showed a new scaling path forward: scale the body thickness in proportion to gate length.
25 citations
01 Dec 2012
TL;DR: A novel process to etch away the defective Ge near Ge/Si interface from epitaxial Ge grown on SOI achieves a nearly defect-free channel, good gate control triangular gate, and larger effective width.
Abstract: Due to the highest electron mobility (2200 cm2/Vs) on (111) Ge surface, the n-channel triangular Ge gate-all-around (GAA) FET with (111) sidewalls on Si and L g =350 nm shows 2x enhanced I on of 110 μA/μm at 1V with respect to the devices with near (110) sidewalls. A novel process to etch away the defective Ge near Ge/Si interface from epitaxial Ge grown on SOI achieves a nearly defect-free channel, good gate control triangular gate, and larger effective width. Electrostatic control of SS= 94 mV/dec (at 1V) can be further improved if superior gate stack than EOT= 5.5 nm and D it = 1×1012 cm−2eV−1 is used. The I on can be further enhanced if the line edge roughness (LER) can be reduced. The Ge GAA n-FET is reported for the first time with CMOS compatible process, which makes the circuits integration much easier.
19 citations
01 Dec 2012
TL;DR: In this article, the gate dielectric has a leakage current ∼104X lower than other reported dielectrics in this EOT region, and the biaxial tensile strain of ∼0.04% applied on Ge (111) nMOSFET with an EOT=0.78nm produces a 4.8% drain current enhancement along the channel.
Abstract: 0.39-nm ultrathin EOT ZrO 2 having κ value as high as ∼43 without an interfacial layer (IL) is demonstrated on Ge substrates. The EOT and gate leakage are much lower than the recent reported data [1]. In situ NH 3 /H 2 remote plasma treatment (RPT) after RTO-grown ultrathin ( 2 /Ge and prior to PEALD ZrO 2 leads to the formation of tetragonal phase ZrO 2 and the inhibition of GeO x IL regrowth. As the number of RPT cycles increases, it is observed that not only higher [N] but more GeO 2 component formed on Ge surface. GeO diffuses into ZrO 2 layer via the interface reaction (Ge+GeO 2 → 2GeO) and stabilize the tetragonal phase ZrO 2 . The gate dielectric has a leakage current ∼104X lower than other reported dielectrics in this EOT region. Ge (001) pMOSFET has low SS of 85 mV/dec and high I on /I off of ∼6×105 at V d = −1V, while nMOSFET has SS of 90 mV/dec and I on /I off of ∼1×105 at V d =1V. The peak electron mobility is determined by the remote phonon scattering stemming from the high-κ value. The biaxial tensile strain of ∼0.04% applied on Ge (111) nMOSFET with an EOT=0.78nm produces a 4.8% drain current enhancement along the channel.
19 citations
01 Dec 2012
TL;DR: In this paper, the difference in the nature of parasitic capacitance in FinFETs and Planar MOSFET is discussed, and its significant impact on circuit performance is discussed.
Abstract: Power dissipation and power density are limiting the maximum operating frequency of highperformance circuits. This has forced a change in the micro-architecture of processors. High frequency, complex single-core architectures are replaced by simpler multi-core architectures that operate at a lower frequency (Fig.1) [1–4]. At sub-22nm nodes, cooling even the multi-core processors using economical cooling options will be challenging due to increasing power density. Hence, there is an imminent need to identify sources with potential to address this issue at the device level so that the benefits can propagate to the circuit level. In this work, we discuss the difference in the difference in the nature of parasitic capacitance in FinFETs and Planar MOSFETs, and its significant impact on circuit performance. Ultra-Thin Body SOI (UTBSOI) MOSFETs [5] is used as an example for Planar MOSFETs.
18 citations
Proceedings Article•
01 Sep 2012Abstract: A new design for negative capacitance FET (NCFET) is proposed. Simulation using 2-D drift-diffusion and 1-D Landau Model exhibits hysteresis free ID-VG transfer characteristic with low subthreshold swing (28.3mV/decade over six-orders-ofmagnitude current change). Without considering mobility enhancement by strain, non-hysteretic NCFET can achieve ION of 333 μA/μm at 0.3V VDD (IOFF=10pA/μm). Keywordsnegative capacitance; NCFET; ferroelectric; FeFET
01 Jan 2012
TL;DR: In this paper, a 3D stackable and bidirectional threshold vacuums switching (TVS) selector using the same WO x material as the RRAM element is reported, which provides the highest reported current density of >108 A/cm2 and the highest selectivity of >105.
Abstract: A 3D stackable and bidirectional Threshold Vacuum Switching (TVS) selector using the same WO x material as the RRAM element is reported. It provides the highest reported current density of >108 A/cm2 and the highest selectivity of >105. Stress test at high current density indicates >108 cycle capability for Reset/Set operation. A mechanism based on recombination of oxygen-ions and vacancies is proposed for the observed volatile switching of TVS. Utilizing the threshold characteristics of the TVS selector, a two-step reading waveform offers potential for 3D-stackable and 4F2 cross-point RRAM applications.
02 Jul 2012
TL;DR: In this paper, the authors proposed a scaling path to scale the body thickness in proportion to gate length, which is similar to the scaling path of FinFETs for near-threshold circuits.
Abstract: FinFET provides needed relief to ICs from performance, power, and device variation predicaments. It also provides higher carrier mobility, especially at low voltage near the threshold voltage, giving promise to practical near-threshold circuits. Another new transistor conceived simultaneously with FinFET, UTB-SOI FET, is also entering production. Together they showed a new scaling path forward: scale the body thickness in proportion to gate length.
01 Dec 2012
TL;DR: In this article, a low temperature microwave annealing (MWA) was used for the first time to realize Ge CMOS with all thermal processes performed by MWA, and the full MWA process is under 390 oC. Compared to conventional RTA, the MWA gives 50% and 24% drive current enhancement for p-and n-MOSFET, respectively.
Abstract: For the first time, Ge CMOS with all thermal processes performed by microwave annealing (MWA) has been realized. The full MWA process is under 390 oC. It significantly outperforms conventional rapid thermal annealing (RTA) process in 3 aspects: (1) Diffusion-less junction: for easily diffused n-type dopant, phosphorous (P), the ion implantation dopant profile after the MWA activation process remains unchanged. (2) Increased C ox and lower gate leakage: the low temperature activation process leads to less Ge out-diffusion during MWA than RTA, suppressing the degradation of gate dielectric/ Ge channel interface. (3) Ultrathin 7.5nm Ni mono-germanide with low sheet resistance (Rs) and contact resistivity: after two-step MWA, a thin mono-NiGe layer was obtained which has larger crystallite size to lower Rs. Ge n- and p-MOSFET were also demonstrated. Compared to conventional RTA, the MWA gives 50% and 24% drive current enhancement for p- and n-MOSFET, respectively. These data show that the low temperature MWA is a very promising thermal process technology for Ge CMOS manufacturing.
15 Oct 2012
TL;DR: This procedure is applicable to any MOSFET compact model with all necessary RF-related components in it and has been validated on silicon data from multiple technology nodes for a wide range of bias and frequency.
Abstract: We present a non-iterative and physical five-step RF SPICE model extraction procedure. This procedure is applicable to any MOSFET compact model with all necessary RF-related components in it. This methodology has been validated on silicon data from multiple technology nodes for a wide range of bias and frequency.
17 Aug 2012
TL;DR: The BSIM6 Model as mentioned in this paper is the next generation Bulk RF MOSFET model and has been tested in DC, small signal, transient and RF simulation and shows excellent convergence in circuit simulation.
Abstract: BSIM6 Model is the next generation Bulk RF MOSFET Model. Model uses charge based core with all physical models adapted from BSIM4 model. Model fulfills all quality tests e.g. Gummel symmetry and AC symmetry test and shows correct slopes for harmonic balance simulation. Model has been tested in DC, small signal, transient and RF simulation and shows excellent convergence in circuit simulation. Model is under standardization at Compact Model Council.
TL;DR: In this article, the effects of surface treatment before the cap dielectric deposition on low-k surface damage and Cu surface cleaning were systematically investigated, and the results showed that the optimized NH"3 plasma condition such as high RF power and high pressure exhibited the high efficiency for oxygen removal from the Cu surface without increasing the k-value of low k film.
01 Dec 2012
TL;DR: In this paper, a sequentially processed 3D hybrid chip is demonstrated by stacking low-temperature Ferroelectric-like (FE-like) metal-oxide nonvolatile memory (NVM) and CMOS.
Abstract: For the first time, a sequentially processed 3D hybrid chip is demonstrated by stacking low-temperature (LT) Ferroelectric-like (FE-like) metal-oxide nonvolatile memory (NVM) and CMOS. The high-mobility (333 and 113 cm2/V-s) and low-subthreshold swing (97 and 112 mV/decade) N/P-type thin film transistors (TFTs) construct stacked inverters showing sharp transfer characteristic as the fundamental element of CMOS array and stacked 3D NVMs. The sequential layered integration is enabled by cutting-edge low thermal-budget plasma/laser processes and self-assembled FE-like metal-oxide materials. The implementation of sub-400oC new-type metal-ion (Eu+3)-mediated atomic-polar-structured (Eu+3-APS) dielectric realizes stackable FE-like NVMs with program speed of 100 nanosecond, toward future 3D layered CMOS with giant high-speed data-storage application era.
01 Dec 2012
TL;DR: The BSIM-IMG is a Turnkey, Production Ready model for FDSOI/UTBSOI devices as discussed by the authors, which is submitted to the CMC for standardization.
Abstract: □ BSIM-IMG is a Turnkey, Production Ready model □ Will be submitted to the CMC for standardization □ Physical, Scalable Core Model for FDSOI devices □ Plethora of Real Device Effects modeled □ Advanced Device Effects — Quantum, Back-gate bias, Self-heating □ Validated on Hardware Data from two FDSOI/ UTBSOI technologies □ Available in major EDA tools.
12 Nov 2012
TL;DR: In this paper, a charge-based compact model BSIM6 has been developed, which is able to handle all the different operating regions of the MOS transistor in the whole geometry range of one technology.
Abstract: The aggressive downscaling of advanced bulk CMOS technologies demands MOSFET models that are able to describe accurately the behavior of devices accounting for all the physical phenomena. A reliable model should have the ability to handle all the different operating regions of the MOS transistor in the whole geometry range of one technology. Targeting to meet the aforementioned needs, the new charge-based compact model BSIM6 has been developed. In this article, as a first benchmarking of BSIM6, the model is evaluated for its scaling capabilities when a single set of parameters is used. The model is compared against a state-of-the-art 40nm CMOS technology. The results attest the model's scalability under all bias conditions, proving its reliability for nowadays complex IC designs.
12 Nov 2012
TL;DR: As a first benchmarking of BSIM6, the model is evaluated for its scaling capabilities when a single set of parameters is used, and the results attest the model's scalability under all bias conditions, proving its reliability for nowadays complex IC designs.
Abstract: The aggressive downscaling of advanced bulk CMOS technologies demands MOSFET models that are able to describe accurately the behavior of devices accounting for all the physical phenomena. A reliable model should have the ability to handle all the different operating regions of the MOS transistor in the whole geometry range of one technology. Targeting to meet the aforementioned needs, the new charge-based compact model BSIM6 has been developed. In this article, as a first benchmarking of BSIM6, the model is evaluated for its scaling capabilities when a single set of parameters is used. The model is compared against a state-of-the-art 40nm CMOS technology. The results attest the model's scalability under all bias conditions, proving its reliability for nowadays complex IC designs.
Proceedings Article•
IBM1
Abstract: A novel geometrically scalable, phenomenological model for quantum mechanical carrier charge centroid in thin fins is presented. A model for capturing the capacitance characteristics of a graded double-junction arising out of punchthrough stop implant in bulk-FinFETs is also proposed. Developed models have been included in BSIM-CMG multi-gate transistor compact model.
Proceedings Article•
01 Sep 2012TL;DR: In this article, the authors used vacuum spacer instead of nitride spacer to reduce the fringing gate capacitance, which results in significant speed increase and energy consumption reduction.
Abstract: Up to 44% reduction in switching energy or 22% reduction in ring oscillator delay time are obtained in simulations by FinFET gate spacer optimization. Using vacuum spacer instead of nitride spacer required for future self-aligned contact technology, the fringing gate capacitance can be lowered by 15%, which results in significant speed increase and energy consumption reduction. The speed benefit can be leveraged to further lower the supply voltage and energy consumption. The vacuum spacer can provide relief to this trend. Keywords-Vacuum Spacer; Air Spacer; Spacer Optimization; FinFET; Multi-Gate; CMOS
06 May 2012
TL;DR: In this paper, the authors report a self-powered TFT panel (30×40 cm2) by integration of sputtering/non-toxic Se vapor selenization copper-indium-gallium-selenide (CIGS) solar cell (conversion efficiency of 8%) and high electron-mobility (172 cm2/V-s) micro-crystalline (μc)-Si TFTs.
Abstract: For the first time, we report a novel self-powered TFT panel (30×40cm2) by integration of sputtering/non-toxic Se vapor selenization copper-indium-gallium-selenide (CIGS) solar cell (conversion efficiency of 8%) and high electron-mobility (172 cm2/V-s) micro-crystalline (μc)-Si TFTs.
TL;DR: In this article, the authors proposed a fast method to extract the density of responsible contact traps, which is attributed to the barrier modification by positive charge trapping and detrapping in a Schottky contact.
Abstract: The behavior of random telegraph noise was affected by nickel silicide barrier height engineering in advanced nano-CMOS technologies. Contact resistance fluctuations with magnitude of up to 40% were observed when a Schottky barrier was reduced to 0.2 eV. The large contact resistance instability is attributed to the barrier modification by positive charge trapping and detrapping in a Schottky contact. The prevalence and magnitude of the noise are dependent on the contact area, trap density, trap energy, and the silicide Schottky barrier height. In this letter, we propose a fast method to extract the density of responsible contact traps.
12 Jun 2012
TL;DR: In this article, a self-aligned, maskless, dual-channel, and metal-gate-based thin-film transistor nano-wire FET was used to achieve record DNA sensitivity.
Abstract: This is the first study to successfully achieve record DNA sensitivity (sub-ƒM) by self-aligned, maskless, dual-channel, and metal-gate-based thin-film transistor nano-wire FET. Both novel device architecture (dual-channel) and optimization of integration processes (microcrystalline silicon and self-aligned sidewall sub-50 nm critical dimension) of nano-wire FET enhance the sensitivity to biological entities substantially. Meanwhile, the proposed device is accomplished with an embedded VLSI CMOS circuit. It can thus offer high application potential to pH, protein, and DNA probing in SoC-based portable bioelectronics.
01 Dec 2012
TL;DR: In this article, a hybrid image sensing and energy harvesting technology is proposed for multi-functional panels with a stacked Si/CIS/Si solar cell design that provides 16.4% efficient bifacial operation.
Abstract: Hydrogen-plasma-enhanced Se vapor selenization is used to produce efficient Na-free CuInSe 2 (CIS) sensor and solar cell, and low temperature plasma-deposited Si thin film solar cell and transistor with 400 cm2/V-s mobility are stacked on top the CIS layer. For the first time, we report a novel stacked Si/CIS/Si solar cell design that provides 16.4%-efficient bifacial operation. Back-side Si solar cell is also an effective UV-visible band filter reducing light degradation and environmental noise on CIS image sensor. This hybrid image sensing and energy-harvesting technology is intended for applications in multi-functional panel with CIS performing both stacked solar cell and stacked TFT/sensor functions but in separate areas.
17 Aug 2012
TL;DR: In this article, an analytical calculation for surfacepotential in UTBSOI MOSFETs is presented, which can be calculated with independent back-gate control, and the accuracy of surface potential calculation is of the order of nano-volts for full range of bias voltage.
Abstract: We present an analytical calculation for surfacepotential in UTBSOI MOSFETs. The developed surfacepotential calculation advances the previous work in terms of computational efficiency and accuracy. The surfacepotential can be calculated with independent back-gate control which is an important requirement for UTBSOI devices. The accuracy of our surface-potential calculation is of the order of nano-volts for full range of bias voltage without use of any empirical or fitting parameter.