Showing papers by "Chenming Hu published in 2019"

Spatially resolved steady-state negative capacitance.

Abstract: Negative capacitance is a newly discovered state of ferroelectric materials that holds promise for electronics applications by exploiting a region of thermodynamic space that is normally not accessible1–14. Although existing reports of negative capacitance substantiate the importance of this phenomenon, they have focused on its macroscale manifestation. These manifestations demonstrate possible uses of steady-state negative capacitance—for example, enhancing the capacitance of a ferroelectric–dielectric heterostructure4,7,14 or improving the subthreshold swing of a transistor8–12. Yet they constitute only indirect measurements of the local state of negative capacitance in which the ferroelectric resides. Spatial mapping of this phenomenon would help its understanding at a microscopic scale and also help to achieve optimal design of devices with potential technological applications. Here we demonstrate a direct measurement of steady-state negative capacitance in a ferroelectric–dielectric heterostructure. We use electron microscopy complemented by phase-field and first-principles-based (second-principles) simulations in SrTiO3/PbTiO3 superlattices to directly determine, with atomic resolution, the local regions in the ferroelectric material where a state of negative capacitance is stabilized. Simultaneous vector mapping of atomic displacements (related to a complex pattern in the polarization field), in conjunction with reconstruction of the local electric field, identify the negative capacitance regions as those with higher energy density and larger polarizability: the domain walls where the polarization is suppressed. Imaging steady-state negative capacitance in SrTiO3/PbTiO3 superlattices with atomic resolution provides solid microscale support for this phenomenon.

Negative Capacitance FET With 1.8-nm-Thick Zr-Doped HfO 2 Oxide

Abstract: We report on negative capacitance FETs (NCFETs) with a 1.8-nm-thick Zr-doped HfO2 gate oxide layer fabricated on an FDSOI wafer. Hysteresis-free operation is demonstrated. When compared to a baseline that uses HfO2 gate oxide with the same thickness, a subthreshold swing (SS) steeper by more than 20 mV/decade and larger than 10X reduction in the OFF current ( ${I}_{ \mathrm{OFF}}$ ) is observed at 30-nm channel length at constant ${I}_{ \mathrm{\scriptscriptstyle ON}}$ . On the other hand, at matched ${I} _{ \mathrm{\scriptscriptstyle OFF}}$ , the NCFET provides a larger ON current at constant ${V}_{\mathrm {DD}}$ . Our results indicate that the beneficial characteristic offered by the NCFETs can be obtained at scaled channel lengths, while using oxide layers whose thickness is comparable to the high- ${K}$ oxide layer used in ultra-scaled nodes.

Proposal for Capacitance Matching in Negative Capacitance Field-Effect Transistors

Abstract: Negative-capacitance transistors use ferroelectric (FE) material in the gate-stack to improve the transistor performance. The extent of the improvement depends on the capacitance matching between the FE capacitance ( ${C}_{\textsf {fe}}$ ) and the underlying MOS transistor ( ${C}_{\textsf {MOS}}$ ). Since both ${C}_{\textsf {MOS}}$ and ${C}_{\textsf {fe}}$ have strong non-linearity, it is difficult to achieve a good matching for the entire operating gate voltage range. In this letter, we discuss a new approach using multi-layer FE to engineer the shape of ${C}_{\textsf {fe}}$ . The proposed method is validated using the TCAD simulation of negative-capacitance FDSOI transistor, and the results show that it leads to better sub-threshold swing as well as lower power supply ${V}_{\textsf {dd}}$ compared with a prototype single-layer negative-capacitance field-effect transistor.

Spacer Engineering in Negative Capacitance FinFETs

Abstract: The spacer design of the negative-capacitance FinFET (NC-FinFET) is investigated by using Sentaurus technology computer-aided design (TCAD). The spacer affects not only the gate capacitance but also the drain current due to the additional gate control from the outer fringing field. It is found that in a heavily loaded circuit although the fin corner spacer improves the inverter propagation delay of the baseline FinFET, the NC-FinFET requires the fin selective spacer with the spacer height up to the ferroelectric thickness for better capacitance matching. When the wire capacitance is ~3 times larger than the gate capacitance, the inverter propagation delay of the NC-FinFET with the fin selective spacer can be improved by ~8% against the full spacer design. However, with the consideration of process complexity, the air spacer may still be attractive in the NC-FinFET, since it does not suffer from the amplified gate capacitance.

Analysis and Modeling of Inner Fringing Field Effect on Negative Capacitance FinFETs

Abstract: We investigate the impact of inner fringing fields on the negative capacitance FinFET (NC-FinFET) and how this scales with the technology node. The 8-/7-nm technology node of the p-type body NC-FinFET is modeled using the Sentaurus technology-aided design (TCAD), which couples Poisson with Landau equations. It is found that the NC effect is beneficial for device scaling. The OFF current is well suppressed in short-channel devices (64.4% reduction at LG = 16 nm) because the inner fringing field induces negative gate charges and decreases the channel potential. For longer channel devices, the influence of inner fringing field disappears, and the depletion charges dominate the subthreshold characteristics. As reducing remnant polarization, the ON current is boosted (11.4% improvement at LG = 16 nm) for all lengths due to better matching between MOSFET and ferroelectric capacitances. In comparison with FinFET, the drain-induced barrier lowering of NC-FinFET is also well controlled (50% reduction at LG = 16 nm) due to the inner fringing field-induced gate charges, showing the scaling capability of NC-FinFET. Furthermore, a compact model to capture the spatial distribution of the inner fringing field is also proposed based on the Gaussian quadrature method, and it is validated with the TCAD simulated data with multiple gate lengths and remnant polarizations.

Effects of Annealing on Ferroelectric Hafnium–Zirconium–Oxide-Based Transistor Technology

Abstract: In this letter, we investigate annealing effects in ferroelectric HfZrO x dielectric in metal–insulator–metal devices and metal–oxide–semiconductor capacitors by comparing two annealing methods: rapid thermal annealing (RTA) and microwave annealing (MWA). The tradeoff characteristics between the annealing conditions, polarization–electric field characteristics, gate leakage current, and interface state density ( ${D} _{\textsf {it}}$ ) are discussed. We show that: 1) a positive correlation between the remanent polarization (Pr), the gate leakage current, and ${D}_{\textsf {it}}$ as the annealing temperature (RTA) and the annealing power (MWA) increase and 2) the MWA is promising for ferroelectric transistors technology, since its low thermal budget can minimize ${D}_{\textsf {it}}$ and avoid increase in the gate leakage current.

Evaluation of NC-FinFET Based Subsystem-Level Logic Circuits

Abstract: This paper examines metal–ferroelectric–insulator–semiconductor negative-capacitance FinFET (NC-FinFET) based VLSI subsystem-level logic circuits. For the first time, with the aid of a short-channel NC-FinFET compact model, we confirm the functionality and evaluate the standby-power/switching-energy/delay performance of large logic circuits (e.g., dynamic 4-bit Manchester carry-chain adder and the formal hierarchical 32-bit carry-look-ahead adder) employing 14-nm ultra-low-power NC-FinFETs. Our study indicates that the inverse V ds-dependence of threshold voltage ( V T), also known as the negative drain-induced barrier lowering, of negative-capacitance field-effect transistor is not only acceptable but also beneficial for the speed performance of both the static and pass-transistor logic (PTL) circuits, especially for the PTL at low V DD.

Monolithic 3D BEOL FinFET switch arrays using location-controlled-grain technique in voltage regulator with better FOM than 2D regulators

Abstract: Monolithic 3D back-end of line (BEOL) FinFET switch arrays are demonstrated in large single crystalline Si islands (2.56 μm2), whose location, size and shape are determined by design. Details of the improved location-controlled-grain (LCG) technique are presented. A voltage regulator implemented with the BEOL switch arrays using external control signals shows better theoretical figure of merit (FOM) of 0.089ns than 2D voltage regulators of 0.43ns.

Challenges to Partial Switching of Hf 0.8 Zr 0.2 O 2 Gated Ferroelectric FET for Multilevel/Analog or Low-Voltage Memory Operation

Abstract: The ability to partially switch an FeFET could enable their use as an embedded low-voltage memory and as analog weight storage in artificial neural networks (ANNs). We report on memory characterization of FeFETs gated with 5.5-nm Hf0.8Zr0.2O2, fabricated on fully depleted silicon-on-insulator using a self-aligned, gate last process. We find that for a single device, excellent elevated temperature retention, program/erase endurance, and read endurance are obtained; however, there is significant device to device variability in the response of the ferroelectric to a partially switching program pulse, which may require the use of feedback in programming.

BSIM-HV: High-Voltage MOSFET Model Including Quasi-Saturation and Self-Heating Effect

Abstract: A BSIM-based compact model for a high-voltage MOSFET is presented. The model uses the BSIM-BULK (formerly BSIM6) model at its core, which has been extended to include the overlap capacitance due to the drift region as well as quasi-saturation effect. The model is symmetric and continuous, is validated with the TCAD simulations and experimental 35- and 90-V LDMOS and 40-V VDMOS transistors, and shows excellent agreement.

Characterization and Modeling of Flicker Noise in FinFETs at Advanced Technology Node

Abstract: 1/ ${f}$ noise is characterized on thick and thin-gate oxide-based FinFETs for different channel lengths. The devices exhibit gate bias dependence in 1/ ${f}$ noise even in the weak-inversion region of operation which cannot be explained by the existing flicker noise model. We attribute this phenomenon to the non-uniform oxide-trap distribution in energy or space. Based on our characterization results for n- and p-channel FinFETs, we have improved the BSIM-CMG industry standard compact model for the FinFETs. The improved model is able to capture the 1/ ${f}$ noise behavior over a wide range of biases, channel lengths, fin numbers, and number of fingers.

Anomalously Beneficial Gate-Length Scaling Trend of Negative Capacitance Transistors

Abstract: The Negative Capacitance Field Effect Transistors exhibit excellent SS and DIBL improvements from the control MOSFET devices at very short gate lengths, a phenomenon which cannot be explained using conventional MOSFET theory. This benefit arises from an effect which acts similarly to decreasing the equivalent-oxide thickness at short gate lengths. The effect is observed in both TCAD simulations and experiments, and is explained by the conjunction of the source/drain inner fringing field and the nonlinear polarizability of ferroelectric materials. The results present a sharp contrast to conventional scaling theory and bode well for extending the MOSFET gate length scaling limit.

Optimization of NCFET by Matching Dielectric and Ferroelectric Nonuniformly Along the Channel

Abstract: A new design to overcome the nonuniformity of capacitance matching along the channel of a negative capacitance field-effect transistor is presented in this letter. By introducing nonuniform oxidation, the thickness of SiO2 at the edge regions of the channel can be increased while maintaining the thickness of SiO2 at the center region of the channel. As a result, the capacitance along the channel becomes more uniform, and better capacitance matching between the dielectric and ferroelectric can be achieved. The Sentaurus TCAD results show improvement of matching in the center region and a significant boost of ON-current (20% improvement).

Monolithic 3D SRAM-CIM Macro Fabricated with BEOL Gate-All-Around MOSFETs

Abstract: For the first time, below 400°C-fabricated gate-all-around (GAA) transistor fabrication process was demonstrated with monolithic computing-in-memory (CIM) circuit. Key enablers are plasma-assisted atomic layer etching (PA-ALE), plasma immersion ion implantation (PIII) and far-infrared laser activation (FIR-LA). The 3D stackable single-grained Si GAA MOSFETs thus fabricated exhibit record-high I on /I off ratio (~108) with low I off (pFETs<10–2 nA/μm). Moreover, the stackability of the GAA MOSFETs and the differential output of dual-mode 10T SRAM readout enable 2x throughput in the CIM circuitry.

Accurate and Computationally Efficient Modeling of Nonquasi Static Effects in MOSFETs for Millimeter-Wave Applications

Abstract: A lumped-circuit nonquasi-static (NQS) model, that is applicable for both large-signal transient simulations and a small-signal ac analysis, is developed in this paper. An improved physical equivalent circuit, capturing NQS effects in the millimeter waveband, is derived using a transmission line model, by incorporating the high-frequency longitudinal gate electrode and a channel distributed RC network. The proposed model is implemented in a BSIM-BULK MOSFET model and validated with dc and RF data, obtained from technology computer-aided design device simulations and experimental data. The proposed model is in very good agreement with the data up to ${50}{f}_{t}$ . The transient currents, for a gate-voltage switching rate of ${5}\times {10}^{{10}}$ V/s, show excellent match with the data. The dc, transient, and ac simulations using the proposed model are much faster than a 10-segmented MOSFET model. This shows that the proposed model is better than other computationally complex compact models, for most RF applications.

Improved Modeling of Bulk Charge Effect for BSIM-BULK Model

Abstract: In this brief, we present an improved model of bulk charge effect for both drain current ( ${I}_{\text {DS}}$ ) and capacitances and its implementation in the industry standard Berkeley short-channel IGFET model (BSIM)-BULK model. The proposed model captures all the well-known and important bulk charge effects, as the Abulk term does for BSIM3/BSIM4. The model is validated with the experimental and technology computer-aided design (TCAD) data. The proposed model enhances the fitting accuracy for ${I}_{\text {DS}}$ , and more importantly its derivatives and capacitances too.

BSIM-BULK: Accurate Compact Model for Analog and RF Circuit Design

Abstract: In this work, we present the recent and upcoming enhancements of the industry standard BSIM-BULK (formerly BSIM6) model. BSIM-BULK is the latest body referenced compact model for bulk MOSFETs having a unified core, which is developed by the BSIM group for accurate design of analog and RF circuits. The model satisfies the symmetry test for DC and AC, correctly predicts harmonic slope, and exhibits accurate results for RF and analog simulations. In order to further improve the model accuracy for transconductance $(g_{m})$ and output conductance $(g_{ds})$, an analytical model for bulk charge effect, in both current and capacitance, is implemented. Several other advanced models are added to capture real device physics. These include: parasitic current at the shallow trench isolation edges; leakage current components in zero threshold voltage native devices; new model for NQS to capture the NQS effects up to the millimeter wave regime; self heating effect; and heavily halo implanted MOSFET’s anomalous g m , flicker noise and I DS mismatch. All these enhancements have been implemented to high standards of computational efficiency and robustness.

Ferroelectric Si-doped HfO 2 Capacitors for Next-Generation Memories

Abstract: In this work, we assess the viability of a CMOS-compatible ferroelectric material, silicon-doped hafnium oxide (Si-HfO 2 ), for future capacitor-based ferroelectric memories by investigating process development, structural/electrical characterization, and memory device benchmarking. Ferroelectric capacitors with iridium electrodes and Si-HfO 2 thicknesses from 8 nm down to 4 nm are fabricated. The Si-HfO 2 layer is grown by atomic layer deposition (ALD) and subjected to a variety of post-processing annealing conditions. Polarization-voltage (PV) loops are taken to extract ferroelectric parameters such as remanent polarization $(\mathrm{P}_{\mathrm{R}})$ and coercive field (Ec), and standard memory tests for fatigue/endurance, retention, and imprint are conducted.

Author Correction: Spatially resolved steady-state negative capacitance

Abstract: In this Letter, the first name of author Bhagwati Prasad was misspelled Bhagawati. This error has been corrected online.

Modeling the Quantum Gate capacitance of Nano-Sheet Gate-All-Around MOSFET

Abstract: Lateral nanosheet field-effect-transistor (FET) is now targeting for 3nm CMOS technology node [1], [2]. It is important to see quantization effect at such confined geometry. In this work, we study the geometrical confinement effects in silicon nanosheet. We developed a unified phenomenological model for insulator capacitance (C ins ) in rectangular (i.e., Nanosheet) cross-section gate-all-around (GAA) FET to solve the gate charge density accurately. It is observed that multi-subband conduction causes humps in higher order derivatives of charge vs gate voltage characteristics which may affect the performance of analog and RF circuits.

Transient Thermal Damage Simulation for Novel Location-Controlled Grain Technique in Monolithic 3D IC

Abstract: In this research, Finite Element Method (FEM) is used to simulate transient thermal conduction in the monolithic three-dimensional integrated circuit (3DIC) with a novel location-controlled-grain (LCG) technique. Through this method, the impact of laser flux, amorphous Si thickness and interlayer dielectric (ILD) thickness on that model can be investigated. Furthermore, with the assistance of thermal damage simulation, we can utilize the optimal process parameters in this state-of-the-art technique to accelerate the development of advanced semiconductor technologies.

Core Model for Independent Multigate MOSFETs

Abstract: This chapter presents the core model for the industry standard compact model BSIM-IMG, a fully featured turn-key compact model for independent multigate MOSFETs. The two independent (front and back gates) controls of the channel charge in these devices enable novel applications wherein the back gate can be in depletion or inversion, and BSIM-IMG accurately models these scenarios. Modeling of the channel charge in this device requires a consistent solution of coupled Poisson’s equations at the front and the back gate. This chapter presents an analytical solution for the Poisson’s equation which is numerically robust and passes important quality tests for an industry grade compact model. To represent real device effects, several extra models are later incorporated, such as drain-induced barrier lowering, velocity saturation, short-channel effects, self-heating effect, mobility-field dependence, and substrate-depletion effect.