Showing papers by "Chenming Hu published in 2021"

Ferroelectric HfO 2 Memory Transistors With High- κ Interfacial Layer and Write Endurance Exceeding 10 10 Cycles

Abstract: We demonstrate ferroelectric (FE) memory transistors on a crystalline silicon channel with endurance exceeding 1010 cycles. The ferroelectric transistors (FeFETs) incorporate a high- $\kappa $ interfacial layer (IL) of thermally grown silicon nitride (SiNx) and a thin 4.5 nm layer of Zr-doped FE-HfO2 (HZO) on a ~30 nm silicon on insulator (SOI) channel. The device shows a ~1V memory window (MW) in a DC sweep of just ± 2.5V, and can be programmed and erased with voltage pulses of $\text {V}_{\text {G}}= \pm \,\,3\text{V}$ at a pulse width of 250 ns. The device also shows very good retention behavior. These results indicate that appropriate engineering of the IL layer could substantially improve FeFET device performance and reliability.

Compact Modeling of Temperature Effects in FDSOI and FinFET Devices Down to Cryogenic Temperatures

Abstract: We present compact models that capture published cryogenic temperature effects on silicon carrier mobility and velocity saturation, as well as fully depleted silicon on insulator (FDSOI) and fin field effect transistor (FinFET) devices characteristics within the industry-standard Berkeley short-channel IGFET model (BSIM) framework for cryogenic IC applications such as quantum computing. For the core model charge density/surface potential calculation, we introduce an effective temperature formulation to capture the effects of the band tail states. We also present a compact model that corrects the low-temperature threshold voltage for the band-tail states, Fermi–Dirac statistics, and interface traps. New temperature-dependent mobility and velocity saturation models are accurate down to cryogenic temperature. In addition, we propose that experimentally observed ${I}_{D}$ dependence of subthreshold swing (SS) at cryogenic temperatures is a consequence of the expectedly higher rate of Coulomb scattering of free carriers.

A Compact Model of Polycrystalline Ferroelectric Capacitor

Abstract: We present a compact model of polycrystalline ferroelectric (FE) capacitors. The polycrystalline thin-film material is modeled as a collection of independent grains or grain groups. Each grain or grain group is characterized by its local field-dependent switching rate, which is characterized by a distribution function such as Gaussian or type-2 generalized beta distribution. This computationally efficient model accurately reproduces the published experimental polarization switching waveforms and the switching current waveforms in response to all reported applied voltage waveforms. The model tracks the polarization history so that it can simulate the transition between major and minor and among minor loops as well as accumulative polarization which cannot be captured by the conventional models. This model is intended for simulating circuits containing FE capacitors using commercial SPICE simulators for arbitrary applied voltage waveforms. It also has the capability of simulating the discrete switching and device variability in small-area FE capacitors having a small number of grains, although there is no available experimental data to check the model accuracy in this regard.

Impacts of surface nitridation on crystalline ferroelectric phase of Hf1-xZrxO2 and ferroelectric FET performance

Abstract: This paper presents an approach to enhance Hf0.5Zr0.5O2 (HZO) ferroelectric orthorhombic phase (O-phase) formation via in situ NH3 plasma treatment. High-resolution non-disruptive hard x-ray photoelectron spectroscopy confirmed that O-phase formation can be enhanced by suppressed interfacial diffusion between HZO and the top TiN electrode. Additional N-bonding facilitated by NH3 treatment was shown to suppress the interaction between TiN and HZO, thereby reducing the formation of oxygen vacancies within HZO. It was shown to improve the reliability and ferroelectric performance (examined by the leakage current and positive-up-negative-down measurements) of HZO devices. After cyclic operations, NH3-treated ferroelectric FETs (FeFETs) exhibited stable transfer characteristics and memory windows, whereas untreated devices presented unstable behaviors. Our results demonstrate the efficacy of the proposed in situ NH3-treatment scheme in enhancing the stability of HZO-based FeFETs.

Negative capacitance enables GAA scaling VDD to 0.5 V

Abstract: We present a TCAD simulation of the negative capacitance gate-all-around (NCGAA) field-effect transistor with the 3-D Ginzburg-Landau-Khalatnikov Model. The baseline device is based on the 2020 IRDS Table, and the mobility model is calibrated to account for ballistic transport and to match the “1.5 nm node” IRDS on-current requirement. The NC parameters are extracted from experimental C-V data. The NC-GAA shows reduction in the off current by one order of magnitude and a 40% on-current boost. If the gate work function is shifted to align the NC-GAA’s off-current with the IRDS high performance requirement, it is shown that NC-GAA can achieve the on-current and VDD requirement of every node through the “0.7 eq node,” which is the last node predicted in the 2020 IRDS Table. Furthermore, NC-GAA can even achieve a “0.5 eq node,” which is three additional nodes beyond the baseline “1.5 nm node.” We also show that these benefits are retained over a varying set of ferroelectric parameters.

Electric Field-Induced Permittivity Enhancement in Negative-Capacitance FET

Abstract: Measurements on ultrathin body negative-capacitance (NC) field-effect transistors are shown to display subthreshold behaviors that cannot be explained as a classical MOSFET. Subthreshold swing (SS) at low drain bias decreases with increased gate bias for devices measured over multiple gate lengths down to 30 nm. In addition, improvement in the SS relative to control devices shows a nonmonotonic dependence on the gate length. Using a Landau–Khalatnikov ferroelectric (FE) model calibrated with measured Capacitance-Voltage and combining it with TCAD simulations, we show that these anomalous behaviors can be quantitatively explained and interpreted as field-induced permittivity enhancement. The model predicts substantial scaling improvement at the end of the roadmap.

Visualizing Ferroelectric Uniformity of Hf1- xZr xO2Films Using X-ray Mapping

Abstract: Hf1-xZrxO2 (HZO) is a complementary metal-oxide-semiconductor (CMOS)-compatible ferroelectric (FE) material with considerable potential for negative capacitance field-effect transistors, ferroelectric memory, and capacitors. At present, however, the deployment of HZO in CMOS integrated circuit (IC) technologies has stalled due to issues related to FE uniformity. Spatially mapping the FE distribution is one approach to facilitating the optimization of HZO thin films. This paper presents a novel technique based on synchrotron X-ray nanobeam absorption spectroscopy capable of mapping the three main phases of HZO (i.e., orthorhombic (O), tetragonal (T), and monoclinic (M)). The practical value of the proposed methodology when implemented in conjunction with kinetic-nucleation modeling is demonstrated by our development of a T → O annealing (TOA) process to optimize HZO films. This process produces an HZO film with the largest polarization values (Ps = 64.5 μC cm-2; Pr = 35.17 μC cm-2) so far, which can be attributed to M-phase suppression followed by low-temperature annealing for the induction of a T → O phase transition.

Atomic-scale ferroic HfO2-ZrO2 superlattice gate stack for advanced transistors

Abstract: With the scaling of lateral dimensions in advanced transistors, an increased gate capacitance is desirable both to retain the control of the gate electrode over the channel and to reduce the operating voltage. This led to the adoption of high-κ dielectric HfO2 in the gate stack in 2008, which remains as the material of choice to date. Here, we report HfO2-ZrO2 superlattice heterostructures as a gate stack, stabilized with mixed ferroelectric-antiferroelectric order, directly integrated onto Si transistors and scaled down to ~ 20 Å, the same gate oxide thickness required for high performance transistors. The overall EOT (equivalent oxide thickness) in metal-oxide-semiconductor capacitors is equivalent to ~ 6.5 Å effective SiO2 thickness, which is, counterintuitively, even smaller than the interfacial SiO2 thickness (8.0-8.5 Å) itself. Such a low effective oxide thickness and the resulting large capacitance cannot be achieved in conventional HfO2-based high-κ dielectric gate stacks without scavenging the interfacial SiO2, which has adverse effects on the electron transport and gate leakage current. Accordingly, our gate stacks, which do not require such scavenging, provide substantially lower leakage current and no mobility degradation. Therefore, our work demonstrates that HfO2-ZrO2 multilayers with competing ferroelectric-antiferroelectric order, stabilized in the 2 nm thickness regime, provides a new path towards advanced gate oxide stacks in electronic devices beyond the conventional HfO2-based high-κ dielectrics.

Single-Crystal Islands (SCI) for Monolithic 3-D and Back-End-of-Line FinFET Circuits

Abstract: A single-crystal islands (SCI) technique using low thermal budget pulse laser process is proposed and demonstrated to fabricate single-crystal silicon islands over amorphous dielectric for monolithic 3-D and back-end-of-line (BEOL) FinFET circuits. By laser recrystallizing mask-defined a-Si islands encapsulated with conformal silicon nitride film, designed single-crystal Si islands can be obtained. The single crystallinity of the island are verified with SECCO Etch, high-resolution electron microscopy (HREM), transmission electron microscopy (TEM), and electron backside scattering (EBSD). About 40 nm FinFETs were successfully fabricated in the SCI Si islands and shown to exhibit excellent electrical performance and low variability that are compatible with the FinFETs fabricated on commercial silicon-on-insulator (SOI) wafer.

Energy Storage and Reuse in Negative Capacitance

Abstract: In this article, we analyze how a ferroelectric (FE) acts as a rechargeable energy storage medium which stores, releases, and retrieves energy, and helps the gate achieve a desired charge density with reduced energy (voltage) from the external gate drive During transistor turn-on, the FE releases energy, while the whole system is absorbing energy, and during turn-off, the FE retrieves energy, while the whole system is releasing energy Capacitor energy is analyzed using two different approaches: static material free energy integrals and transient circuit power integrals The two results agree within 1% Energy analysis is also performed for a metal–oxide–semiconductor field-effect transistor structure for two gate lengths, 20 nm and $2~\mu \text{m}$ , in an inverter circuit At 2- $\mu \text{m}$ gate length, the values of energy match under these two different approaches with less than a 6% difference The difference is larger in the 20-nm gate length case due to larger parasitic capacitances, such as gate-to-drain and gate-to-source capacitance, affecting the transient circuit analysis Even so, most of the energy storage and retrieval benefit is retained even in small size negative capacitance transistors

S-Curve Engineering for ON-State Performance Using Anti-Ferroelectric/Ferroelectric Stack Negative-Capacitance FinFET

Abstract: This work investigates the S-curve engineering by exploiting the anti-ferroelectric (AFE)/ferroelectric (FE) stack negative-capacitance FinFET (NC-FinFET) to improve both the subthreshold swing and ON-state current ( $I_{\text {ON}}$ ). The capacitance matching and ON-state performance are evaluated using a short-channel AFE/FE stack NC-FinFET model. Our study indicates that the AFE/FE gate-stack can theoretically achieve surprising improvements to the OFF-state current ( $I_{\text {OFF}}$ ) and $I_{\text {ON}}$ relative to International Roadmap for Devices and Systems (IRDS) projections. There is a significant long-term advantage to integrated circuit (IC) power consumption and speed if materials with certain AFE and FE characteristics can be developed and introduced into IC manufacturing.

Ferroelectric HfO$_2$ Memory Transistors with High-$\kappa$ Interfacial Layer and Write Endurance Exceeding $10^{10}$ Cycles

Abstract: We demonstrate ferroelectric (FE) memory transistors on a crystalline silicon channel with endurance exceeding $10^{10}$ cycles. The ferroelectric transistors (FeFETs) incorporate a high-$\kappa$ interfacial layer (IL) of thermally grown silicon nitride (SiN$_x$) and a thin 4.5 nm layer of Zr-doped FE-HfO$_2$ on a $\sim$30 nm SOI channel. The device shows a $\sim$ 1V memory window in a DC sweep of just $\pm$ 2.5V, and can be programmed and erased with voltage pulses of $V_G= \pm$ 3V at a pulse width of 250 ns. The device also shows very good retention behavior. These results indicate that appropriate engineering of the IL layer could substantially improve FeFET device performance and reliability.