Chenming Hu

Bio: Chenming Hu is an academic researcher from University of California, Berkeley. The author has contributed to research in topics: MOSFET & Gate oxide. The author has an hindex of 119, co-authored 1296 publications receiving 57264 citations. Previous affiliations of Chenming Hu include Motorola & National Chiao Tung University.

Thickness and other effects on oxide and interface damage by plasma processing

Abstract: The authors point out that plasma induced oxide charging occurs mainly during the overetch time. There is no measurable additional damage during the moment of plasma turn-on and turn-off. Plasma acts more like a current source than a voltage source. This is fortunate for future thinner oxides. There is a latent interface damage remaining after the forming gas anneal. A discrepancy between the defect densities measured in test structures and in circuits is explained. >

Comparison of short-channel effect and offstate leakage in symmetric vs. asymmetric double gate MOSFETs

Abstract: Double gate MOSFETs (DGFETs) in the sub-0.1 /spl mu/m regime are unlikely to use channel doping to set the threshold voltage, V/sub t/. Therefore, work function engineering is required to properly set V/sub t/. Asymmetric DGFETs use one n/sup +/ and one p/sup +/-poly gate to achieve a reasonable threshold voltage (Tanaka et al., 1994), whereas symmetric DGFETs use the same near-midgap material for both gates. This results in significantly different energy-band diagrams. The on-state drive currents in these two structures have been shown to be comparable to each other if off-state leakage currents are balanced; in the on-state, the asymmetric DGFET matches the inherent two-channel advantage of the symmetric DGFET with a single dynamic-threshold channel (Kim and Fossum, 1999). However, their short-channel effects should differ, since the two structures have different leakage paths. In this paper, the MEDICI 2D device simulator is used to study off-state leakage current in NMOS DGFETs as a function of channel length. The short-channel leakage behavior is explained by analyzing the change in the channel potential barrier.

Octagonal washer DC SQUIDs and integrated susceptometers fabricated in a planarized sub- mu m Nb-AlO/sub x/-Nb technology

Abstract: The authors have designed, fabricated, and measured a number of Nb-AlO/sub x/-Nb octagonal washer DC superconducting quantum interference devices (SQUIDs) and miniature DC SQUID susceptometers having minimum feature size down to 0.5 mu m. With SQUID inductance values on the order of 100 pH, typical noise performance is better than 1 mu Phi /sub 0// square root Hz. The small minimum feature size of input coils and pickup loop structures will facilitate tight coupling to a wide variety of systems ranging from submicron particles and structures to conventional approximately mu H input circuits. A single-washer SQUID with an 80-turn 0.5- mu m-linewidth, 630-nH input coil has user-friendly V- Phi (voltage-flux) curves and a coupled energy sensitivity of 20 h at 4.2 K. Susceptometers with pickup loops ranging from 20- mu m to 0.8- mu m across have very user-friendly V- Phi curves and a resolution of order 100 mu /sub B// square root Hz at 4.2 K for devices with the smallest loops. >

Conductive channel in ONO formed by controlled dielectric breakdown

Abstract: Cross-section TEM photos that capture the conductive channel of oxide-nitride-oxide (ONO) films after electric breakdown are discussed. The photos reveal a single crystal or polycrystal channel with a dome-shaped cap depending on the breakdown current. The implications of this structure for electric characteristics is analyzed with a spherical thermal-electric model. When ONO films are used as antifuse on FPGA product, the resistance of the antifuse can be controlled by choosing a sufficiently large programming current level and the resistance remains stable during 1000 h of burn-in at 125 degrees C and 5.75 V. Negligible change in delay time along many different data paths was observed. >

Design Optimization Techniques in Nanosheet Transistor for RF Applications

Abstract: Nanosheet gate-all-around transistors are analyzed for RF applications using calibrated TCAD simulations. The effects of stack spacing and number of stacks on device performance are studied and a substack design for improved RF performance is proposed. The novel substack design can improve cut-off frequency ( ${F}_{{t}}$ ) by ~10% and minimum number of substacks and minimum substack spacing should be used.

I and i

Abstract: There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality. Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

疟原虫var基因转换速率变化导致抗原变异[英]／Paul H, Robert P, Christodoulou Z, et al//Proc Natl Acad Sci U S A

Abstract: 抗原变异可使得多种致病微生物易于逃避宿主免疫应答。表达在感染红细胞表面的恶性疟原虫红细胞表面蛋白1（PfPMP1）与感染红细胞、内皮细胞、树突状细胞以及胎盘的单个或多个受体作用，在黏附及免疫逃避中起关键的作用。每个单倍体基因组var基因家族编码约60种成员，通过启动转录不同的var基因变异体为抗原变异提供了分子基础。

High-κ gate dielectrics: Current status and materials properties considerations

Abstract: Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.1 μm complementary metal–oxide–semiconductor (CMOS) technology. A systematic consideration of the required properties of gate dielectrics indicates that the key guidelines for selecting an alternative gate dielectric are (a) permittivity, band gap, and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. A review of current work and literature in the area of alternate gate dielectrics is given. Based on reported results and fundamental considerations, the pseudobinary materials systems offer large flexibility and show the most promise toward success...

Design of Analog CMOS Integrated Circuits

Abstract: The CMOS technology area has quickly grown, calling for a new text--and here it is, covering the analysis and design of CMOS integrated circuits that practicing engineers need to master to succeed. Filled with many examples and chapter-ending problems, the book not only describes the thought process behind each circuit topology, but also considers the rationale behind each modification. The analysis and design techniques focus on CMOS circuits but also apply to other IC technologies. Table of contents 1 Introduction to Analog Design 2 Basic MOS Device Physics 3 Single-Stage Amplifiers 4 Differential Amplifiers 5 Passive and Active Current Mirrors 6 Frequency Response of Amplifiers 7 Noise 8 Feedback 9 Operational Amplifiers 10 Stability and Frequency Compensation 11 Bandgap References 12 Introduction to Switched-Capacitor Circuits 13 Nonlinearity and Mismatch 14 Oscillators 15 Phase-Locked Loops 16 Short-Channel Effects and Device Models 17 CMOS Processing Technology 18 Layout and Packaging

Prospects of Colloidal Nanocrystals for Electronic and Optoelectronic Applications

Abstract: Nanocrystals (NCs) discussed in this Review are tiny crystals of metals, semiconductors, and magnetic material consisting of hundreds to a few thousand atoms each. Their size ranges from 2-3 to about 20 nm. What is special about this size regime that placed NCs among the hottest research topics of the last decades? The quantum mechanical coupling * To whom correspondence should be addressed. E-mail: dvtalapin@uchicago.edu. † The University of Chicago. ‡ Argonne National Lab. Chem. Rev. 2010, 110, 389–458 389