Chenming Hu

Bio: Chenming Hu is an academic researcher from University of California, Berkeley. The author has contributed to research in topics: MOSFET & Gate oxide. The author has an hindex of 119, co-authored 1296 publications receiving 57264 citations. Previous affiliations of Chenming Hu include Motorola & National Chiao Tung University.

Performance and reliability comparison between asymmetric and symmetric LDD devices and logic gates

Abstract: The performance and reliability of NMOSFET asymmetric lightly doped drain (LDD) devices (with no LDD on the source side) are compared with those of conventional LDD devices. At a fixed V/sub dd/, asymmetric LDD devices exhibit higher I/sub dsat/ and shorter hot-carrier lifetime. To maintain the same hot-carrier lifetime, asymmetric LDD devices must operate at lower V/sub dd/ while higher I/sub dsat/ is retained. For the same hot-carrier lifetime, ring oscillators with NMOSFET asymmetric LDD devices can achieve 5% (10% if PMOSFET also had asymmetric LDD) higher speed and 10% lower power. The hot-carrier reliability of inverter, NAND, and NOR structures with asymmetric and conventional LDD devices is also simulated and compared.

Improving the Electrical Properties of NILC Poly-Si Films Using a Gettering Substrate

Abstract: Ni-metal-induced lateral crystallization (NILC) of amorphous silicon (alpha-Si) has been employed to fabricate poly-crystalline silicon (poly-Si) thin-film transistors. However, current crystallization technology often leads to Ni and NiSi2 precipitates being trapped, thus degrading the performance of the device. We proposed using alpha-Si-coated wafers as Ni-gettering substrates. After bonding the gettering substrate with the NILC poly-Si film, both the Ni-metal impurity within the NILC poly-Si film and the leakage current were greatly reduced, thus increasing the ON/OFF current ratio.

Investigation of poly-Si/sub 1-x/Ge/sub x/ for dual-gate CMOS technology

Abstract: Poly-Si/sub 1-x/Ge/sub x/-gated MOS capacitors were fabricated with x varying from 0 to 0.5. NMOS and PMOS C-V characteristics were measured. Reduced poly-gate depletion effect (PDE) was observed in PMOS devices with increasing Ge mole fraction; while for NMOS, devices with a Ge content /spl sim/20% exhibit the least PDE. Higher active dopant concentration and reduced gate-depletion width for devices featuring less PDE were confirmed. Work function difference (/spl Phi//sub MS/) was found to decrease slightly in N/sup +/ films and significantly in P/sup +/ films as Ge content increases. The shift in /spl Phi//sub MS/ for N/sup +/ poly-Si/sub 1-x/Ge/sub x/ is negligible while it is -0.13 V for P/sup +/Si/sub 0.8/Ge/sub 0.2/ and -0.32 V for P/sup +/Si/sub 0.5/Ge/sub 0.5/. The reduction in energy bandgap (/spl Delta/E/sub g/) was also determined to increase from 0 to 0.26 eV as Ge content increases from 0 to 50%. For deep submicron dual-gate CMOS application, the shift in /spl Phi//sub MS/ should be minimized for low and symmetrical V/sub th/ as well as improved short-channel effect (SCE). A Ge content of /spl sim/20% therefore seems to offer the best tradeoff between SCE and PDE.

A new bi-directional PMOSFET hot-carrier degradation model for circuit reliability simulation

Abstract: In this paper, the concept of channel shortening is used to model hot-carrier induced PMOSFET drain current degradation. This new approach models the asymmetric drain current degradation in forward and reverse modes of operation and provides the capability to simulate bi-directional stress. We will present the model, its implementation in BERT (BErkeley Reliability Tools), and simulation results of uni- and bi-directionally stressed circuits. >

BSIM5 MOSFET Model

Abstract: This paper summarizes BSIM5 MOSFET model for aggressively scaled CMOS technology which was released recently. Various new physical effects are timely addressed in the new physical core including more accurate physics that is easily extended to non-charge-sheet, completely continuous current and derivatives, and extendibility to non-traditional CMOS based devices including SOI and double-gate MOSFETs. The flexible architecture also enables the carry-over of BSFM4's accurate modeling of numerous device behaviors attributable to device physics or technologies.

I and i

Abstract: There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality. Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

疟原虫var基因转换速率变化导致抗原变异[英]／Paul H, Robert P, Christodoulou Z, et al//Proc Natl Acad Sci U S A

Abstract: 抗原变异可使得多种致病微生物易于逃避宿主免疫应答。表达在感染红细胞表面的恶性疟原虫红细胞表面蛋白1（PfPMP1）与感染红细胞、内皮细胞、树突状细胞以及胎盘的单个或多个受体作用，在黏附及免疫逃避中起关键的作用。每个单倍体基因组var基因家族编码约60种成员，通过启动转录不同的var基因变异体为抗原变异提供了分子基础。

High-κ gate dielectrics: Current status and materials properties considerations

Abstract: Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.1 μm complementary metal–oxide–semiconductor (CMOS) technology. A systematic consideration of the required properties of gate dielectrics indicates that the key guidelines for selecting an alternative gate dielectric are (a) permittivity, band gap, and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. A review of current work and literature in the area of alternate gate dielectrics is given. Based on reported results and fundamental considerations, the pseudobinary materials systems offer large flexibility and show the most promise toward success...

Design of Analog CMOS Integrated Circuits

Abstract: The CMOS technology area has quickly grown, calling for a new text--and here it is, covering the analysis and design of CMOS integrated circuits that practicing engineers need to master to succeed. Filled with many examples and chapter-ending problems, the book not only describes the thought process behind each circuit topology, but also considers the rationale behind each modification. The analysis and design techniques focus on CMOS circuits but also apply to other IC technologies. Table of contents 1 Introduction to Analog Design 2 Basic MOS Device Physics 3 Single-Stage Amplifiers 4 Differential Amplifiers 5 Passive and Active Current Mirrors 6 Frequency Response of Amplifiers 7 Noise 8 Feedback 9 Operational Amplifiers 10 Stability and Frequency Compensation 11 Bandgap References 12 Introduction to Switched-Capacitor Circuits 13 Nonlinearity and Mismatch 14 Oscillators 15 Phase-Locked Loops 16 Short-Channel Effects and Device Models 17 CMOS Processing Technology 18 Layout and Packaging

Prospects of Colloidal Nanocrystals for Electronic and Optoelectronic Applications

Abstract: Nanocrystals (NCs) discussed in this Review are tiny crystals of metals, semiconductors, and magnetic material consisting of hundreds to a few thousand atoms each. Their size ranges from 2-3 to about 20 nm. What is special about this size regime that placed NCs among the hottest research topics of the last decades? The quantum mechanical coupling * To whom correspondence should be addressed. E-mail: dvtalapin@uchicago.edu. † The University of Chicago. ‡ Argonne National Lab. Chem. Rev. 2010, 110, 389–458 389