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Chenming Hu
Researcher at University of California, Berkeley
Publications - 1300
Citations - 60963
Chenming Hu is an academic researcher from University of California, Berkeley. The author has contributed to research in topics: MOSFET & Gate oxide. The author has an hindex of 119, co-authored 1296 publications receiving 57264 citations. Previous affiliations of Chenming Hu include Motorola & National Chiao Tung University.
Papers
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Journal ArticleDOI
Transient behavior of subthreshold characteristics of fully depleted SOI MOSFETs
TL;DR: In this article, the subthreshold currents of fully depleted silicon-on-insulator (SOI) MOSFETs show a transient behavior under certain front-gate and back-gate voltage conditions.
Proceedings ArticleDOI
A 65nm node strained SOI technology with slim spacer
Fu-Liang Yang,Chien-Chao Huang,Hou-Yu Chen,Jhon-Jhy Liaw,Tang-Xuan Chung,Hung-Wei Chen,Chang-Yun Chang,Cheng Chuan Huang,Kuang-Hsin Chen,Di-Hong Lee,Hsun-Chih Tsao,Cheng-Kuo Wen,Shui-Ming Cheng,Yi-Ming Sheu,Ke-Wei Su,Chi-Chun Chen,Tze-Liang Lee,Shih-Chang Chen,C.H. Chen,Cheng-hung Chang,Jhi-cheng Lu,W. Chang,Chuan-Ping Hou,Ying-Ho Chen,Kuei-Shun Chen,Ming Lu,Li-Wei Kung,Yu-Jun Chou,Fu-Jye Liang,Jan-Wen You,King-Chang Shu,Bin-Chang Chang,Jaw-Jung Shin,Chun-Kuang Chen,Tsai-Sheng Gau,Bor-Wen Chan,Yi-Chun Huang,Han-Jan Tao,J.H. Chen,Yung-Shun Chen,Yee-Chia Yeo,Samuel Fung,Carlos H. Diaz,Chii-Ming Wu,Burn-Jeng Lin,Liang Min-Chang,J.Y.-C. Sun,Chenming Hu +47 more
TL;DR: In this article, a 65 nm node strained SOI technology with high performance is demonstrated, providing drive currents of 1015 and 500 /spl mu/A/A//spl µ/m for N-FETs and P-Fet, respectively, at an off-state leakage of 40 nA/spl μ/m using 1 V operation.
Proceedings ArticleDOI
Reliability of thin SiO/sub 2/ at direct-tunneling voltages
TL;DR: In this article, the authors investigated the factors that impact thickness scaling of silicon dioxide gate insulators in VLSI technology at low voltages, and the direct-tunneling mechanism was shown to result in oxide leakage current orders of magnitude higher than predicted by Fowler-Nordheim theory.
Proceedings ArticleDOI
BSIM model for circuit design using advanced technologies
TL;DR: BSIM (Berkeley Short-channel IGFET Model) enables circuit designers to accurately simulate CMOS circuits by including gate tunneling, quantum effect, and RF effects.
Journal ArticleDOI
Circuit-level simulation of TDDB failure in digital CMOS circuits
TL;DR: An efficient circuit-level simulator for the prediction of time-dependent dielectric breakdown effects in digital CMOS circuits has been developed and integrated into the reliability simulation tool BERT (Berkeley Reliability Tools) as mentioned in this paper.