Chenming Hu

Bio: Chenming Hu is an academic researcher from University of California, Berkeley. The author has contributed to research in topics: MOSFET & Gate oxide. The author has an hindex of 119, co-authored 1296 publications receiving 57264 citations. Previous affiliations of Chenming Hu include Motorola & National Chiao Tung University.

Compact Model for Geometry Dependent Mobility in Nanosheet FETs

Abstract: We propose an updated compact model for mobility in Nanosheet FETs. This is necessary since Nanosheet FETs exhibit significant mobility degradation with thickness and width scaling caused by centroid shift, changing effective mass due to quantum confinement as well as various crystal orientations of the various conduction planes. The model takes all of these effects into account. It has been implemented in Verilog-A and validated with experimental data. To the best of our knowledge, this is the first compact model capturing the effect of nanosheet scaling on mobility.

Dummy pattern for silicide gate electrode

Abstract: A semiconductor device having a plurality of silicided polysilicon structures in which the silicidation of the polysilicon structures is approximately uniform is provided. Dummy polysilicon structures are formed on the substrate prior to silicidation. The dummy polysilicon structures allow the surface of the wafer to be planarized without an excessive recess and causes the amount of metal available for the silicidation process to be approximately uniformly distributed among the various polysilicon structures.

Interfacial layer-free ZrO 2 on Ge with 0.39-nm EOT, κ∼43, ∼2×10 −3 A/cm 2 gate leakage, SS =85 mV/dec, I on /I off =6×10 5 , and high strain response

Abstract: 0.39-nm ultrathin EOT ZrO 2 having κ value as high as ∼43 without an interfacial layer (IL) is demonstrated on Ge substrates. The EOT and gate leakage are much lower than the recent reported data [1]. In situ NH 3 /H 2 remote plasma treatment (RPT) after RTO-grown ultrathin ( 2 /Ge and prior to PEALD ZrO 2 leads to the formation of tetragonal phase ZrO 2 and the inhibition of GeO x IL regrowth. As the number of RPT cycles increases, it is observed that not only higher [N] but more GeO 2 component formed on Ge surface. GeO diffuses into ZrO 2 layer via the interface reaction (Ge+GeO 2 → 2GeO) and stabilize the tetragonal phase ZrO 2 . The gate dielectric has a leakage current ∼104X lower than other reported dielectrics in this EOT region. Ge (001) pMOSFET has low SS of 85 mV/dec and high I on /I off of ∼6×105 at V d = −1V, while nMOSFET has SS of 90 mV/dec and I on /I off of ∼1×105 at V d =1V. The peak electron mobility is determined by the remote phonon scattering stemming from the high-κ value. The biaxial tensile strain of ∼0.04% applied on Ge (111) nMOSFET with an EOT=0.78nm produces a 4.8% drain current enhancement along the channel.

Method of fabricating a self-aligned high speed MOSFET device

Abstract: A high speed MOSFET device includes a punchthrough stopper region in the channel of the device formed by high energy ion implantation through the gate electrode and self-aligned therewith. The device has reduced capacitance. A self-aligned recessed channel MOSFET structure includes the punchthrough stopper region to further improve short channel device behavior.

Charge-based core and the model architecture of BSIM5

Abstract: The paper outlines the charge-based core and the architecture of the BSIM5 MOSFET model for sub-100 nm CMOS circuit simulation. The BSIM5 model is a continuous, completely symmetric and accurate non charge-sheet based MOS transistor model derived from the basic device physics, including various physics effects. Comparison of the inversion charge between the BSIM5 prediction and self-consistent numerical solution shows good agreement. The demonstration of fully symmetric characteristics of BSIM5, such as channel current and its high-order derivative in the Gummel symmetry test, and charge and trans-capacitances in a SPICE simulation, also implies BSIM5 is the physically symmetric MOSFET model valid for RF-analog circuit simulations.

I and i

Abstract: There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality. Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

疟原虫var基因转换速率变化导致抗原变异[英]／Paul H, Robert P, Christodoulou Z, et al//Proc Natl Acad Sci U S A

Abstract: 抗原变异可使得多种致病微生物易于逃避宿主免疫应答。表达在感染红细胞表面的恶性疟原虫红细胞表面蛋白1（PfPMP1）与感染红细胞、内皮细胞、树突状细胞以及胎盘的单个或多个受体作用，在黏附及免疫逃避中起关键的作用。每个单倍体基因组var基因家族编码约60种成员，通过启动转录不同的var基因变异体为抗原变异提供了分子基础。

High-κ gate dielectrics: Current status and materials properties considerations

Abstract: Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.1 μm complementary metal–oxide–semiconductor (CMOS) technology. A systematic consideration of the required properties of gate dielectrics indicates that the key guidelines for selecting an alternative gate dielectric are (a) permittivity, band gap, and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. A review of current work and literature in the area of alternate gate dielectrics is given. Based on reported results and fundamental considerations, the pseudobinary materials systems offer large flexibility and show the most promise toward success...

Design of Analog CMOS Integrated Circuits

Abstract: The CMOS technology area has quickly grown, calling for a new text--and here it is, covering the analysis and design of CMOS integrated circuits that practicing engineers need to master to succeed. Filled with many examples and chapter-ending problems, the book not only describes the thought process behind each circuit topology, but also considers the rationale behind each modification. The analysis and design techniques focus on CMOS circuits but also apply to other IC technologies. Table of contents 1 Introduction to Analog Design 2 Basic MOS Device Physics 3 Single-Stage Amplifiers 4 Differential Amplifiers 5 Passive and Active Current Mirrors 6 Frequency Response of Amplifiers 7 Noise 8 Feedback 9 Operational Amplifiers 10 Stability and Frequency Compensation 11 Bandgap References 12 Introduction to Switched-Capacitor Circuits 13 Nonlinearity and Mismatch 14 Oscillators 15 Phase-Locked Loops 16 Short-Channel Effects and Device Models 17 CMOS Processing Technology 18 Layout and Packaging

Prospects of Colloidal Nanocrystals for Electronic and Optoelectronic Applications

Abstract: Nanocrystals (NCs) discussed in this Review are tiny crystals of metals, semiconductors, and magnetic material consisting of hundreds to a few thousand atoms each. Their size ranges from 2-3 to about 20 nm. What is special about this size regime that placed NCs among the hottest research topics of the last decades? The quantum mechanical coupling * To whom correspondence should be addressed. E-mail: dvtalapin@uchicago.edu. † The University of Chicago. ‡ Argonne National Lab. Chem. Rev. 2010, 110, 389–458 389