Chenming Hu

Bio: Chenming Hu is an academic researcher from University of California, Berkeley. The author has contributed to research in topics: MOSFET & Gate oxide. The author has an hindex of 119, co-authored 1296 publications receiving 57264 citations. Previous affiliations of Chenming Hu include Motorola & National Chiao Tung University.

Observation of reduced boron penetration and gate depletion for poly-Si/sub 0.8/Ge/sub 0.2/ gated PMOS devices

Abstract: Poly-Si/sub 0.8/Ge/sub 0.2/-and poly-Si-gated PMOS capacitors with very thin gate oxides were fabricated. Boron penetration and poly-gate depletion effects (PDE) in these devices were both analyzed. Observations of smaller flat-band voltage shift and superior gate oxide reliability suggest less boron penetration problem in poly-Si/sub 0.8/Ge/sub 0.2/-gated devices. Higher dopant activation rate, higher active dopant concentration near the poly/SiO/sub 2/ interface and therefore improved PDE were also found in boron-implanted poly-Si/sub 0.8/Ge/sub 0.2/-gated devices as compared to poly-Si-gated devices. A larger process window therefore exists for a poly-Si/sub 0.8/Ge/sub 0.2/ gate technology with regard to the tradeoff between boron penetration and poly-gate depletion.

A 10 nm Si-based bulk FinFETs 6T SRAM with multiple fin heights technology for 25% better static noise margin

Abstract: For the first time, 10nm Si-based bulk FinFETs 6T SRAM (beta ratio = 2) with novel multiple fin heights technology is successfully demonstrated with 25% better static noise margin at 0.6 V than single fin-height baseline. Meanwhile, presented technology also provides advantage in SRAM cell size by 20% scaling down. It can furthermore offer potential of beyond 10nm Si-based CMOS computing circuit technology.

Operation of CMOS devices with a floating well

Abstract: The operation of CMOS devices in an electrically floating well is considered. The impetus for this study is the potential reduction of silicon area consumption and wiring complexity involved in contacting the well diffusion. Theoretical expectations for device behavior are presented and corroborated with experimental data; consideration extends to PMOSFET device characteristics, subthreshold behavior, as well as junction leakage and breakdown voltage. Examination of n-channel devices, in p-wells, indicates that these are more susceptible to floating well effects, as expected. The primary changes in device behavior include generation of substrate current, slight increase in leakage currents, and some degradation in latchup holding voltage. Results indicate that an electrically floating well does not seem to have significant adverse effects on transistor operation.

A little known benefit of FinFET over Planar MOSFET in highperformance circuits at advanced technology nodes

Abstract: Power dissipation and power density are limiting the maximum operating frequency of highperformance circuits. This has forced a change in the micro-architecture of processors. High frequency, complex single-core architectures are replaced by simpler multi-core architectures that operate at a lower frequency (Fig.1) [1–4]. At sub-22nm nodes, cooling even the multi-core processors using economical cooling options will be challenging due to increasing power density. Hence, there is an imminent need to identify sources with potential to address this issue at the device level so that the benefits can propagate to the circuit level. In this work, we discuss the difference in the difference in the nature of parasitic capacitance in FinFETs and Planar MOSFETs, and its significant impact on circuit performance. Ultra-Thin Body SOI (UTBSOI) MOSFETs [5] is used as an example for Planar MOSFETs.

A resonant-cavity, separate-absorption-and-multiplication, avalanche photodiode with low excess noise factor

Abstract: We report on the design, fabrication, and performance of a photodiode that combines the advantages of a resonant cavity with a separate-absorption-and-multiplication avalanche photodiode. The device is grown on GaAs using molecular beam epitaxy and is designed to detect light near 900 nm. This photodetector has exhibited the following characteristics: an external quantum efficiency of 70%, a spectral linewidth of less than 7 nm, an avalanche gain in excess of 30, and low dark current. In addition, a low excess noise factor corresponding to 0.2/spl les/k/spl les/0.3 has been achieved.

I and i

Abstract: There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality. Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

疟原虫var基因转换速率变化导致抗原变异[英]／Paul H, Robert P, Christodoulou Z, et al//Proc Natl Acad Sci U S A

Abstract: 抗原变异可使得多种致病微生物易于逃避宿主免疫应答。表达在感染红细胞表面的恶性疟原虫红细胞表面蛋白1（PfPMP1）与感染红细胞、内皮细胞、树突状细胞以及胎盘的单个或多个受体作用，在黏附及免疫逃避中起关键的作用。每个单倍体基因组var基因家族编码约60种成员，通过启动转录不同的var基因变异体为抗原变异提供了分子基础。

High-κ gate dielectrics: Current status and materials properties considerations

Abstract: Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.1 μm complementary metal–oxide–semiconductor (CMOS) technology. A systematic consideration of the required properties of gate dielectrics indicates that the key guidelines for selecting an alternative gate dielectric are (a) permittivity, band gap, and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. A review of current work and literature in the area of alternate gate dielectrics is given. Based on reported results and fundamental considerations, the pseudobinary materials systems offer large flexibility and show the most promise toward success...

Design of Analog CMOS Integrated Circuits

Abstract: The CMOS technology area has quickly grown, calling for a new text--and here it is, covering the analysis and design of CMOS integrated circuits that practicing engineers need to master to succeed. Filled with many examples and chapter-ending problems, the book not only describes the thought process behind each circuit topology, but also considers the rationale behind each modification. The analysis and design techniques focus on CMOS circuits but also apply to other IC technologies. Table of contents 1 Introduction to Analog Design 2 Basic MOS Device Physics 3 Single-Stage Amplifiers 4 Differential Amplifiers 5 Passive and Active Current Mirrors 6 Frequency Response of Amplifiers 7 Noise 8 Feedback 9 Operational Amplifiers 10 Stability and Frequency Compensation 11 Bandgap References 12 Introduction to Switched-Capacitor Circuits 13 Nonlinearity and Mismatch 14 Oscillators 15 Phase-Locked Loops 16 Short-Channel Effects and Device Models 17 CMOS Processing Technology 18 Layout and Packaging

Prospects of Colloidal Nanocrystals for Electronic and Optoelectronic Applications

Abstract: Nanocrystals (NCs) discussed in this Review are tiny crystals of metals, semiconductors, and magnetic material consisting of hundreds to a few thousand atoms each. Their size ranges from 2-3 to about 20 nm. What is special about this size regime that placed NCs among the hottest research topics of the last decades? The quantum mechanical coupling * To whom correspondence should be addressed. E-mail: dvtalapin@uchicago.edu. † The University of Chicago. ‡ Argonne National Lab. Chem. Rev. 2010, 110, 389–458 389