There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

抗原变异可使得多种致病微生物易于逃避宿主免疫应答。表达在感染红细胞表面的恶性疟原虫红细胞表面蛋白1（PfPMP1）与感染红细胞、内皮细胞、树突状细胞以及胎盘的单个或多个受体作用，在黏附及免疫逃避中起关键的作用。每个单倍体基因组var基因家族编码约60种成员，通过启动转录不同的var基因变异体为抗原变异提供了分子基础。

疟原虫var基因转换速率变化导致抗原变异[英]／Paul H, Robert P, Christodoulou Z, et al//Proc Natl Acad Sci U S A

Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.1 μm complementary metal–oxide–semiconductor (CMOS) technology. A systematic consideration of the required properties of gate dielectrics indicates that the key guidelines for selecting an alternative gate dielectric are (a) permittivity, band gap, and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. A review of current work and literature in the area of alternate gate dielectrics is given. Based on reported results and fundamental considerations, the pseudobinary materials systems offer large flexibility and show the most promise toward success...

/pdf/high-k-gate-dielectrics-current-status-and-materials-zjvba0c4u8.pdf

High-κ gate dielectrics: Current status and materials properties considerations

The CMOS technology area has quickly grown, calling for a new text--and here it is, covering the analysis and design of CMOS integrated circuits that practicing engineers need to master to succeed. Filled with many examples and chapter-ending problems, the book not only describes the thought process behind each circuit topology, but also considers the rationale behind each modification. The analysis and design techniques focus on CMOS circuits but also apply to other IC technologies.
Table of contents

1 Introduction to Analog Design
2 Basic MOS Device Physics
3 Single-Stage Amplifiers
4 Differential Amplifiers
5 Passive and Active Current Mirrors
6 Frequency Response of Amplifiers
7 Noise
8 Feedback
9 Operational Amplifiers
10 Stability and Frequency Compensation
11 Bandgap References
12 Introduction to Switched-Capacitor Circuits
13 Nonlinearity and Mismatch
14 Oscillators
15 Phase-Locked Loops
16 Short-Channel Effects and Device Models
17 CMOS Processing Technology
18 Layout and Packaging

/pdf/design-of-analog-cmos-integrated-circuits-35wxhwa3a6.pdf

Design of Analog CMOS Integrated Circuits

Nanocrystals (NCs) discussed in this Review are tiny crystals of metals, semiconductors, and magnetic material consisting of hundreds to a few thousand atoms each. Their size ranges from 2-3 to about 20 nm. What is special about this size regime that placed NCs among the hottest research topics of the last decades? The quantum mechanical coupling * To whom correspondence should be addressed. E-mail: dvtalapin@uchicago.edu. † The University of Chicago. ‡ Argonne National Lab. Chem. Rev. 2010, 110, 389–458 389

/pdf/prospects-of-colloidal-nanocrystals-for-electronic-and-3dxpyhl3r7.pdf

Prospects of Colloidal Nanocrystals for Electronic and Optoelectronic Applications

An ultra thin MOSFET device structure located on an insulator layer, and a method of forming the ultra thin MOSFET device structure featuring a strained silicon channel located on the underlying insulator layer, has been developed. After epitaxial growth of a semiconductor alloy layer such as silicon-germanium (SiGe), on a first semiconductor substrate, a strained silicon channel layer, under biaxial tensile strain, is epitaxially grown on the underlying semiconductor alloy layer. Bonding of the strained silicon channel layer of the first semiconductor substrate, to a silicon oxide layer located on the surface of a second semiconductor substrate, is followed by a cleaving procedure performed at the interface of the strained silicon channel layer and the underlying semiconductor alloy layer, resulting in the desired configuration comprised of strained silicon channel layer-underlying insulator layer-second semiconductor substrate. The MOSFET device is then formed featuring the strained silicon channel layer, on the underlying silicon oxide layer, with enhanced carrier mobility realized as a result of the biaxial tensile strain of the silicon channel layer.

MOSFET device with a strained channel

A model for dV/dt breakdown in power MOSFET's is proposed. This model allows quantitative analysis of dV/dt limitation in power MOSFET circuits. Experimental results show good agreement with theoretical predictions.

dV/dt Breakdown in power MOSFET's

Novel SOI (Silicon On Insulator) model parameter extraction methodology based on the concept of SHE (Self-Heating Effect) free device modeling, is proposed and demonstrated for a 0.18 /spl mu/m PD (Partially Depleted) SOI technology. In this methodology, prior to SPICE parameter extraction, the device thermal resistances are measured and the current loss due to SHE is added back analytically to DC I-V data. Therefore, the parameters are free from SHE. DC, AC, and transient simulation results using this technology show good agreement with measurement data.

Methodology of self-heating free parameter extraction and circuit simulation for SOI CMOS

A static random access memory array cell that is non-volatile because when power fails a floating gate is charged or not charged depending on the information content of the cell. When power is restored, all cells are written to a positive state except those with charged floating gates so that the information content of the array is recreated.

Nonvolatile memory cell

We describe how x-ray microbeam diffraction is being used to measure strain with micron-scale spatial resolution. Micron-scale x-ray beams can be obtained using tapered glass capillaries. With the high brightness and broad energy spectrum of synchrotron radiation and the energy dispersive capabilities of commercially available, liquid nitrogen cooled x-ray detectors, spatially resolved strains in a sample can be determined along different directions without having to rotate the sample, in contrast with more conventional methods using monochromatic x-ray diffraction. This is a major advantage in achieving micron-scale spatial resolution. Strain sensitivities on the order of 2×10−4 have been achieved in such measurements. White beam x-ray microdiffraction has been applied for the first time in real-time studies of thermal and electromigration related strain distributions in passivated Al-on-Si conductor lines. Results of measurements on a single 10µm- wide line are described.

Chenming Hu

Papers

MOSFET device with a strained channel

dV/dt Breakdown in power MOSFET's

Methodology of self-heating free parameter extraction and circuit simulation for SOI CMOS

Nonvolatile memory cell

X-Ray Microdiffraction for VLSI