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Chenming Hu
Researcher at University of California, Berkeley
Publications - 1300
Citations - 60963
Chenming Hu is an academic researcher from University of California, Berkeley. The author has contributed to research in topics: MOSFET & Gate oxide. The author has an hindex of 119, co-authored 1296 publications receiving 57264 citations. Previous affiliations of Chenming Hu include Motorola & National Chiao Tung University.
Papers
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Proceedings ArticleDOI
BSIM-IMG: Advanced Model for FDSOI Transistors with Back Channel Inversion
Harshit Agarwal,Pragya Kushwaha,Avirup Dasgupta,M. Y-Kao,T. Morshed,G. Workman,K. Shanbhag,X. Li,V. Vinothkumar,Yogesh Singh Chauhan,Sayeef Salahuddin,Chenming Hu +11 more
TL;DR: A new 1/f noise model is presented and the back gate inversion is more physically modeled in the latest BSIM-IMG model for accurate modeling of the FDSOI transistors.
Patent
Necked Finfet device
TL;DR: In this paper, a double gate, FINFET device structure in a silicon on insulator layer, in which the channel region formed in the SOI layer is defined with a narrowed, or necked shape, and wherein a composite insulator spacer is formed on the sides of the device structure, has been developed.
Journal ArticleDOI
Two-dimensional to three-dimensional tunneling in InAs/AlSb/GaSb quantum well heterojunctions
Yuping Zeng,Yuping Zeng,Chien I. Kuo,Rehan Kapadia,Rehan Kapadia,Ching Yi Hsu,Ali Javey,Ali Javey,Chenming Hu +8 more
TL;DR: In this article, a gate controlled tunneling diode with multiple subband contributions is presented. But the performance of the gate-controlled tunneling is limited due to spatial confinement in the 10nm-thick InAs layer.
Proceedings ArticleDOI
3D FinFET and other sub-22nm transistors
TL;DR: In this paper, the authors proposed a scaling path to scale the body thickness in proportion to gate length, which is similar to the scaling path of FinFETs for near-threshold circuits.
Proceedings ArticleDOI
Recess channel structure for reducing source/drain series resistance in ultra-thin SOI MOSFETs
TL;DR: A new Recess-Channel technology has been developed which significantly reduces the source/drain series resistance and is potentially very useful for ultra-thin-film fully depleted SOI MOSFET fabrication with arbitrary silicon film thickness.