Author
Chenming Hu
Other affiliations: Motorola, National Chiao Tung University, Semtech ...read more
Bio: Chenming Hu is an academic researcher from University of California, Berkeley. The author has contributed to research in topics: MOSFET & Gate oxide. The author has an hindex of 119, co-authored 1296 publications receiving 57264 citations. Previous affiliations of Chenming Hu include Motorola & National Chiao Tung University.
Topics: MOSFET, Gate oxide, CMOS, Gate dielectric, Transistor
Papers published on a yearly basis
Papers
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01 Dec 2018
TL;DR: A Monte Carlo TCAD simulation study of the impact of polycrystallinity and dielectric phases of the ferroelectric film on an 8/7 nm node NC-FinFET is presented in this paper.
Abstract: A Monte Carlo TCAD simulation study of the impact of polycrystallinity and dielectric phases of the ferroelectric film on an 8/7 nm node NC-FinFET is presented. The study considers the random variation of ferroelectric remnant polarization $(\boldsymbol{P_{r}})$ and the presence of dielectric phases. In order to keep the ferroelectric-film induced device variability less than those induced by other sources (RDF, GER, FER, and MGG), we found that the DE content must be less than 20%, which is theoretically possible, and the grain to grain $\boldsymbol{P_{r}}$ variations less than 27%. While uniform single-crystalline ferroelectric film would provide the least device variation, we found 4 nm grains to produce less device variability than 5.3 nm grains due to the larger number of grains in the channel area.
14 citations
TL;DR: In this paper, the roles of substrate compensation type, carrier densities and trap parameters in the manifestation of back-gating effects are investigated and simple analytical models and simulation results are presented.
Abstract: Substrate leakage between electrodes and back-gating are two major non-idealities which affect device and circuit performance in GaAs integrated circuits fabricated on semi-insulating substrates. Simple analytical models and simulation results are presented to elucidate the roles of substrate compensation type, carrier densities and trap parameters in the manifestation of these effects. Chrome-doped substrates exhibit long-range negative-bias back-gating because the bias is supported across the channel-substrate junction. Undoped LEC substrates are insensitive to long-range back-gating in either direction unless holes are introduced (e.g. by radiation) or fast transients are present. Above the onset voltage for TFL conduction, both substrates exhibit strong back-gating. While p-wells tied to a voltage source reduce back-gating, floating p-wells or wells shallower than the device n+ implants can significantly worsen back-gating.
14 citations
01 Jan 2001
TL;DR: In this paper, an enhanced impact ionization phenomenon caused by self-heating effect (SHE) in SOI MOSFETs has been reported, which is a source for carrier heating.
Abstract: Impact ionization (II) originates from energetic carriers in the channel The II current is not only a monitor of device reliability, but also affects the current drive of partially-depleted (PD) SOI transistors by charging up the floating body and hence varying the threshold voltage Due to the low thermal conductivity of buried oxide, SOI MOSFETs are susceptible to the local thermal heating generated in the channel This SOI-specific self-heating effect (SHE) provides a source for carrier heating, which may determine impact ionization In this paper we report an enhanced impact-ionization phenomenon caused by SHE in SOI MOSFETs
14 citations
TL;DR: In this article, the Ni-metal impurity within the NILC poly-Si film was reduced without addition mask, and α-Si was coated on the top of contact holes as Ni-gettering layer.
Abstract: Ni-metal-induced lateral crystallization (NILC) of amorphous Si (α-Si) has been used to fabricate high-performance low-temperature polycrystalline silicon (poly-Si) thin-film transistors (TFTs) The current crystallization technology, however, often leads to trap Ni and NiSi2 precipitates, which degrade the device performance In this study, α-Si film was coated on the top of contact holes as Ni-gettering layer It was found the Ni-metal impurity within the NILC poly-Si film was reduced without addition mask
14 citations
17 Jun 2009
TL;DR: In this article, a theoretical model has shown that Cu lifetime in on-chip Damascene interconnect structures has dropped for every new interconnect generation, even when tested at the same current density, and that a mixture of bamboo and polycrystalline grain structures instead of a bamboo-like structure observed for <90nm wide lines (65 nm technology node) resulted in further lifetime degradation by the addition of grain boundary diffusion.
Abstract: Electromigration data and a theoretical model have shown that Cu lifetime in on‐chip Damascene interconnect structures has dropped for every new interconnect generation, even when tested at the same current density In addition, a mixture of bamboo and polycrystalline grain structures instead of a bamboo‐like structure observed for <90 nm wide lines (65 nm technology node) resulted in further lifetime degradation by the addition of grain boundary diffusion The techniques for improving EM lifetime either by modifying the interconnect structure by adding dummy vias on top of a Cu line, a Ru cap on the Cu top surface, or the formation of a thin CuSiN layer at the Cu/dielectric interface were investigated The upper dummy vias, the Ru cap or CuSiN layer on the top surface of the Cu lines interrupted the Cu mass flow along the top surface interface which can improve lifetimes The upper level dummy via structure was a powerful tool for helping to understand the Cu microstructure and to distinguish fast diffus
14 citations
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[...]
TL;DR: There is, I think, something ethereal about i —the square root of minus one, which seems an odd beast at that time—an intruder hovering on the edge of reality.
Abstract: There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.
Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …
33,785 citations
28 Jul 2005
TL;DR: PfPMP1）与感染红细胞、树突状组胞以及胎盘的单个或多个受体作用，在黏附及免疫逃避中起关键的作�ly.
Abstract: 抗原变异可使得多种致病微生物易于逃避宿主免疫应答。表达在感染红细胞表面的恶性疟原虫红细胞表面蛋白1（PfPMP1）与感染红细胞、内皮细胞、树突状细胞以及胎盘的单个或多个受体作用，在黏附及免疫逃避中起关键的作用。每个单倍体基因组var基因家族编码约60种成员，通过启动转录不同的var基因变异体为抗原变异提供了分子基础。
18,940 citations
TL;DR: In this paper, a review of the literature in the area of alternate gate dielectrics is given, based on reported results and fundamental considerations, the pseudobinary materials systems offer large flexibility and show the most promise toward success.
Abstract: Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.1 μm complementary metal–oxide–semiconductor (CMOS) technology. A systematic consideration of the required properties of gate dielectrics indicates that the key guidelines for selecting an alternative gate dielectric are (a) permittivity, band gap, and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. A review of current work and literature in the area of alternate gate dielectrics is given. Based on reported results and fundamental considerations, the pseudobinary materials systems offer large flexibility and show the most promise toward success...
5,711 citations
Book•
01 Jan 1999
TL;DR: The analysis and design techniques of CMOS integrated circuits that practicing engineers need to master to succeed can be found in this article, where the authors describe the thought process behind each circuit topology, but also consider the rationale behind each modification.
Abstract: The CMOS technology area has quickly grown, calling for a new text--and here it is, covering the analysis and design of CMOS integrated circuits that practicing engineers need to master to succeed. Filled with many examples and chapter-ending problems, the book not only describes the thought process behind each circuit topology, but also considers the rationale behind each modification. The analysis and design techniques focus on CMOS circuits but also apply to other IC technologies.
Table of contents
1 Introduction to Analog Design
2 Basic MOS Device Physics
3 Single-Stage Amplifiers
4 Differential Amplifiers
5 Passive and Active Current Mirrors
6 Frequency Response of Amplifiers
7 Noise
8 Feedback
9 Operational Amplifiers
10 Stability and Frequency Compensation
11 Bandgap References
12 Introduction to Switched-Capacitor Circuits
13 Nonlinearity and Mismatch
14 Oscillators
15 Phase-Locked Loops
16 Short-Channel Effects and Device Models
17 CMOS Processing Technology
18 Layout and Packaging
4,826 citations
TL;DR: Nanocrystals (NCs) discussed in this Review are tiny crystals of metals, semiconductors, and magnetic material consisting of hundreds to a few thousand atoms each that are among the hottest research topics of the last decades.
Abstract: Nanocrystals (NCs) discussed in this Review are tiny crystals of metals, semiconductors, and magnetic material consisting of hundreds to a few thousand atoms each. Their size ranges from 2-3 to about 20 nm. What is special about this size regime that placed NCs among the hottest research topics of the last decades? The quantum mechanical coupling * To whom correspondence should be addressed. E-mail: dvtalapin@uchicago.edu. † The University of Chicago. ‡ Argonne National Lab. Chem. Rev. 2010, 110, 389–458 389
3,720 citations