Chenming Hu

Bio: Chenming Hu is an academic researcher from University of California, Berkeley. The author has contributed to research in topics: MOSFET & Gate oxide. The author has an hindex of 119, co-authored 1296 publications receiving 57264 citations. Previous affiliations of Chenming Hu include Motorola & National Chiao Tung University.

Full low temperature microwave processed Ge CMOS achieving diffusion-less junction and Ultrathin 7.5nm Ni mono-germanide

Abstract: For the first time, Ge CMOS with all thermal processes performed by microwave annealing (MWA) has been realized. The full MWA process is under 390 oC. It significantly outperforms conventional rapid thermal annealing (RTA) process in 3 aspects: (1) Diffusion-less junction: for easily diffused n-type dopant, phosphorous (P), the ion implantation dopant profile after the MWA activation process remains unchanged. (2) Increased C ox and lower gate leakage: the low temperature activation process leads to less Ge out-diffusion during MWA than RTA, suppressing the degradation of gate dielectric/ Ge channel interface. (3) Ultrathin 7.5nm Ni mono-germanide with low sheet resistance (Rs) and contact resistivity: after two-step MWA, a thin mono-NiGe layer was obtained which has larger crystallite size to lower Rs. Ge n- and p-MOSFET were also demonstrated. Compared to conventional RTA, the MWA gives 50% and 24% drive current enhancement for p- and n-MOSFET, respectively. These data show that the low temperature MWA is a very promising thermal process technology for Ge CMOS manufacturing.

Compact Modeling of Drain Current Thermal Noise in FDSOI MOSFETs Including Back-Bias Effect

Abstract: In this paper, we present an analytical charge-based model for thermal noise power spectral density in fully depleted silicon on insulator (FDSOI) MOSFETs. Two important aspects particular to FDSOI technology, namely, different inversion charges and different effective mobilities at front and back interfaces, are considered in the model. Proposed model is valid from weak to strong inversion regions of operation. Velocity saturation and channel length modulation are also incorporated to properly capture the excess noise in deep submicrometer MOSFETs. To test the quality of the model, standard benchmark tests are performed and asymptotic behavior of the model is validated in all regions of operation. The model is implemented in SPICE and validated with calibrated TCAD simulations as well as with experimental data of high frequency noise for wide range of back biases.

Improved Cobalt Silicidation Process for Substrates with a Silicon Germanium Layer

Abstract: A method comprises providing a semiconductor alloy layer on a semiconductor substrate, forming a gate structure on the semiconductor alloy layer, forming source and drain regions in the semiconductor substrate on both sides of the gate structure, removing at least a portion of the semiconductor alloy layer overlying the source and drain regions, and forming a metal silicide region over the source and drain regions.

AC Charge Centroid Model For Quantization Of Inversion Layer In N-MOSFET

Abstract: A simulator using coupled Schrodinger equation, Poisson equation and Fermi-Dirac statistics to analyze inversion layer quantization is verified with the measured C-V data of thin oxide MOS capacitors closely. The effects of bias voltage, oxide thickness and doping concentration on the AC charge centroid is presented. A simple empirical model for the AC charge centroid of the inversion layer is proposed. An effective AC thickness is introduced to model the inversion capacitance in both weak and strong inversion regime. This model predlcts the inversion layer capacitance and AC charge centroid in term of Tm, V , , and V, explicitly. Introduction As MOSFETs are scaled to deep sub-micron Qmension, the oxide thickness is correspondingly reduced. In the thin oxide regime (< lOnm) , the effect of channel quantization is increasingly important. Many studies have been presented on the effect of quantization on MOSFET's performance and characterization [1,2]. In the thin oxide regime, a better quantitative understanding of MOS capacitance is increasingly important. Classical model for solving the inversion charge distribution predicts that the charge peaks at the intedace and overestimates the capacitance. Conventional method of oxide thckness estimation using C-V measurement without includtng quantization of the inversion layer results in a higher value of oxide thickness, the electrical thickness. Several correction methods were proposed [3,4], however, these studies lack universal quantitative expression for the correction term. It is known that due to the quantization of the inversion layer, the peak of the charge may be tens of angstroms away from the interface, contrary to the classical solution which suggests that the peak charge density is right at the Si/Si02 surface. Approximate theoretical solution of the Schrodinger and Poisson equations for the average position 11 -A (Q, +--?,) 3[5,6]. However there is no simple analytical model to quantitatively predict the average charge location. In this work, we developed a 1Dimensional simulator that self-consistently solves Schrodinger and Poisson equations and Fermi-Dirac Statistics. We propose an empirical model from the simulation results that can express the AC charge centroid, X , , due to quantization by V,, V,, T, explicitly. Using this simple model, the correction term can be easily applied in engineering practices and to circuit simulation models. suggests X d c -

SiON/Ta/sub 2/O/sub 5//TiN gate-stack transistor with 1.8 nm equivalent SiO/sub 2/ thickness

Abstract: SiON/Ta/sub 2/O/sub 5/ stacked gate dielectric exhibits 3-5 orders smaller leakage current than SiO/sub 2/ at 18 nm, while the transistor characteristics such as mobility, I/sub d/-V/sub g/, and I/sub d/-V/sub d/, are similar to those of SiO/sub 2/ transistor N-channel MOSFET with equivalent SiO/sub 2/ thickness down to 18 nm (14 nm equivalent due to elimination of poly-Si depletion) is demonstrated Process effects are also studied for optimum process condition

I and i

Abstract: There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality. Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

疟原虫var基因转换速率变化导致抗原变异[英]／Paul H, Robert P, Christodoulou Z, et al//Proc Natl Acad Sci U S A

Abstract: 抗原变异可使得多种致病微生物易于逃避宿主免疫应答。表达在感染红细胞表面的恶性疟原虫红细胞表面蛋白1（PfPMP1）与感染红细胞、内皮细胞、树突状细胞以及胎盘的单个或多个受体作用，在黏附及免疫逃避中起关键的作用。每个单倍体基因组var基因家族编码约60种成员，通过启动转录不同的var基因变异体为抗原变异提供了分子基础。

High-κ gate dielectrics: Current status and materials properties considerations

Abstract: Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.1 μm complementary metal–oxide–semiconductor (CMOS) technology. A systematic consideration of the required properties of gate dielectrics indicates that the key guidelines for selecting an alternative gate dielectric are (a) permittivity, band gap, and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. A review of current work and literature in the area of alternate gate dielectrics is given. Based on reported results and fundamental considerations, the pseudobinary materials systems offer large flexibility and show the most promise toward success...

Design of Analog CMOS Integrated Circuits

Abstract: The CMOS technology area has quickly grown, calling for a new text--and here it is, covering the analysis and design of CMOS integrated circuits that practicing engineers need to master to succeed. Filled with many examples and chapter-ending problems, the book not only describes the thought process behind each circuit topology, but also considers the rationale behind each modification. The analysis and design techniques focus on CMOS circuits but also apply to other IC technologies. Table of contents 1 Introduction to Analog Design 2 Basic MOS Device Physics 3 Single-Stage Amplifiers 4 Differential Amplifiers 5 Passive and Active Current Mirrors 6 Frequency Response of Amplifiers 7 Noise 8 Feedback 9 Operational Amplifiers 10 Stability and Frequency Compensation 11 Bandgap References 12 Introduction to Switched-Capacitor Circuits 13 Nonlinearity and Mismatch 14 Oscillators 15 Phase-Locked Loops 16 Short-Channel Effects and Device Models 17 CMOS Processing Technology 18 Layout and Packaging

Prospects of Colloidal Nanocrystals for Electronic and Optoelectronic Applications

Abstract: Nanocrystals (NCs) discussed in this Review are tiny crystals of metals, semiconductors, and magnetic material consisting of hundreds to a few thousand atoms each. Their size ranges from 2-3 to about 20 nm. What is special about this size regime that placed NCs among the hottest research topics of the last decades? The quantum mechanical coupling * To whom correspondence should be addressed. E-mail: dvtalapin@uchicago.edu. † The University of Chicago. ‡ Argonne National Lab. Chem. Rev. 2010, 110, 389–458 389