Chenming Hu

Bio: Chenming Hu is an academic researcher from University of California, Berkeley. The author has contributed to research in topics: MOSFET & Gate oxide. The author has an hindex of 119, co-authored 1296 publications receiving 57264 citations. Previous affiliations of Chenming Hu include Motorola & National Chiao Tung University.

Modeling of Charge and Quantum Capacitance in Low Effective Mass III-V FinFETs

Abstract: In this paper, we present a compact model for semiconductor charge and quantum capacitance in III-V channel FETs. With III-V being viewed as the most promising candidate for future technology node, a compact model is needed for their circuit simulation. The model presented in this paper addresses this need and is completely explicit and computationally efficient which makes it highly suitable for SPICE implementation. The proposed model is verified against the numerical solution of coupled Schrodinger–Poisson equation for FinFET with various channel thickness and effective mass.

Modeling of Back-Gate Effects on Gate-Induced Drain Leakage and Gate Currents in UTB SOI MOSFETs

Abstract: The back-gate bias-dependent gate-induced drain leakage (GIDL) and gate current models of ultrathin body (UTB) silicon-on-insulator (SOI) MOSFETs are proposed. From the experimental data, the GIDL current depends on the back bias due to the electric field change in the channel/drain junction. This effect is modeled using effective gate bias as the threshold voltage shifts. The back-gate bias-dependent gate current is also analyzed and modeled. The voltage across the oxide and available charges for tunneling are the important factors. In accumulation bias condition, the gate leakage is mainly flowing through the overlap region, while in inversion bias condition the current is tunneling from the gate to the channel. Both back bias-dependent GIDL and gate current models are implemented into industry standard compact model Berkeley Short-channel IGFET Model-Independent Multi-Gate for UTB SOI transistors. The model is in good agreement with the experimental data.

Method of fabricating a non-floating body device with enhanced performance

Abstract: Provided is a semiconductor transistor device including a substrate having at least two regions, a semiconductive region extending to a first surface of the substrate and an insulative region extending to a second surface of the substrate. The semiconductor transistor device also includes a patterned semiconductor structure overlying both surfaces of the substrate. The patterned semiconductor structure includes a source or drain region overlying the second surface of the substrate. The semiconductor transistor device further includes a patterned gate structure overlying the patterned semiconductor structure.

A new method of analyzing the short-circuit current of silicon solar cells

Abstract: New approximations for the carrier generation rates in silicon under AM1 and AM2 solar illumination are presented. They may simplify the analysis of silicon solar cells, particularly when done by hand.

Analysis and Modeling of Temperature and Bias Dependence of Current Mismatch in Halo-Implanted MOSFETs

Abstract: We present an analytical model that accurately captures anomalous matching characteristics of drain current in a halo-implanted MOSFET across bias, geometry, and temperature. It is shown that the variation in drain current in different gate bias regimes results from the random-dopant fluctuations (RDFs) in different spatial regions across the channel of the device with nonuniform channel doping. Such effects cannot be captured by existing compact models. Using the impedance field method to calculate the relative contributions of the RDF in the higher doped halo region and the lower doped channel region, we demonstrate, for the first time, an analytical model that can successfully capture the drain current mismatch from subthreshold to strong inversion. We also report for the first time the unique temperature dependence of matching of the drain current in halo-implanted devices and propose a model to capture this behavior. The model is validated using extensive technology computer-aided design analysis and experimental data and is can be extended to the framework of the industry standard BSIM-BULK (formerly BSIM6) MOS model.

I and i

Abstract: There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality. Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

疟原虫var基因转换速率变化导致抗原变异[英]／Paul H, Robert P, Christodoulou Z, et al//Proc Natl Acad Sci U S A

Abstract: 抗原变异可使得多种致病微生物易于逃避宿主免疫应答。表达在感染红细胞表面的恶性疟原虫红细胞表面蛋白1（PfPMP1）与感染红细胞、内皮细胞、树突状细胞以及胎盘的单个或多个受体作用，在黏附及免疫逃避中起关键的作用。每个单倍体基因组var基因家族编码约60种成员，通过启动转录不同的var基因变异体为抗原变异提供了分子基础。

High-κ gate dielectrics: Current status and materials properties considerations

Abstract: Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.1 μm complementary metal–oxide–semiconductor (CMOS) technology. A systematic consideration of the required properties of gate dielectrics indicates that the key guidelines for selecting an alternative gate dielectric are (a) permittivity, band gap, and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. A review of current work and literature in the area of alternate gate dielectrics is given. Based on reported results and fundamental considerations, the pseudobinary materials systems offer large flexibility and show the most promise toward success...

Design of Analog CMOS Integrated Circuits

Abstract: The CMOS technology area has quickly grown, calling for a new text--and here it is, covering the analysis and design of CMOS integrated circuits that practicing engineers need to master to succeed. Filled with many examples and chapter-ending problems, the book not only describes the thought process behind each circuit topology, but also considers the rationale behind each modification. The analysis and design techniques focus on CMOS circuits but also apply to other IC technologies. Table of contents 1 Introduction to Analog Design 2 Basic MOS Device Physics 3 Single-Stage Amplifiers 4 Differential Amplifiers 5 Passive and Active Current Mirrors 6 Frequency Response of Amplifiers 7 Noise 8 Feedback 9 Operational Amplifiers 10 Stability and Frequency Compensation 11 Bandgap References 12 Introduction to Switched-Capacitor Circuits 13 Nonlinearity and Mismatch 14 Oscillators 15 Phase-Locked Loops 16 Short-Channel Effects and Device Models 17 CMOS Processing Technology 18 Layout and Packaging

Prospects of Colloidal Nanocrystals for Electronic and Optoelectronic Applications

Abstract: Nanocrystals (NCs) discussed in this Review are tiny crystals of metals, semiconductors, and magnetic material consisting of hundreds to a few thousand atoms each. Their size ranges from 2-3 to about 20 nm. What is special about this size regime that placed NCs among the hottest research topics of the last decades? The quantum mechanical coupling * To whom correspondence should be addressed. E-mail: dvtalapin@uchicago.edu. † The University of Chicago. ‡ Argonne National Lab. Chem. Rev. 2010, 110, 389–458 389