Chenming Hu

Bio: Chenming Hu is an academic researcher from University of California, Berkeley. The author has contributed to research in topics: MOSFET & Gate oxide. The author has an hindex of 119, co-authored 1296 publications receiving 57264 citations. Previous affiliations of Chenming Hu include Motorola & National Chiao Tung University.

Simulating hot-carrier effects on circuit performance

Abstract: Hot carriers cause charge trapping in the gate oxide of MOSFETs and generate interface traps at Si/SiO2 interfaces of MOSFETs and bipolar transistors. Models for N-channel and P-channel MOSFETs and for bipolar transistor degradations have been developed and implemented in an IC reliability simulator BERT. Several comparisons between simulation results and measurements are shown. There remain to be answered questions concerning the presence of excess degradation when the stressing signal frequency is high.

Effect of copper on the microstructure and electromigration lifetime of Ti–AlCu–Ti fine lines in the presence of tungsten diffusion barriers

Abstract: A systematic study was performed of the microstructural and electromigration characteristics of Ti–Al(Cu)–Ti laminate structures fabricated from two metal wiring levels 1 μm in width. The total Cu content in the Al(Cu) core layers was varied from 0.5 to 2.0 wt %. A high degree of 〈111〉 texture was found for all Cu concentrations except for the 0.5 wt % film. Grain size statistics were found to be independent of the Cu concentration. The Al grains were supersaturated with Cu which led to shifts in resistance during low temperature baking and electromigration testing. The electromigration lifetime of stripes connected to large reservoirs of Cu and Al was found to be linearly dependent on the total Cu content, whereas there was a ‘‘roll off’’ in the lifetime of two‐level W stud structures as the Cu content was increased. The activation energy for electromigration induced failure was found to be 0.78–0.93 eV. Resistance shifts during electromigration and temperature only stressing and the microstructural characteristics of failed structures were explained in terms of the distribution of Cu in the Al matrix and the geometry of the structures using a blocking boundary model.

Velocity overshoot of electrons and holes in Si inversion layers

Abstract: Velocity overshoot of inversion layer electrons and holes is studied experimentally and analytically in special test structures with nominally uniform electric field. The data were used to calibrate energy relaxation parameters in a commercial simulator MEDICI ver. 2.0. We propose an analytical model for velocity overshoot and show that it agrees well with experimental data. The amount of hole velocity overshoot is small.

Lithography and fabrication processes for sub‐100 nm scale complementary metal–oxide semiconductor

Abstract: We explore the fabrication of complementary metal–oxide–semiconductor (CMOS) devices and circuits with a critical dimension of 100 nm and below using a variety of lithographic, processing, materials, and device design innovations. Device design parameters tailored for high performance at low operating power include the use of bulk and silicon‐on‐insulator substrates, a steep retrograde channel doping scheme, ultrathin (∼3 nm) gate dielectric, shallow source, and drain extensions, and a metal‐over‐gate structure. Mix‐and‐match lithography, including the use of electron‐beam lithography for all critical levels, x‐ray lithography for gate level definition, and optical (deep ultraviolet) lithography for noncritical levels, is used in an effort to exploit the strongest features of each of these lithography technologies. New reactive ion etching processes for CMOS gate definition as well as for device and circuit metallization have been developed in conjunction with the lithographic processes in an effort to fa...

Noise modeling and characterization for 1.5-V 1.8-GHz SOI low-noise amplifier

Abstract: SOI technology is a promising candidate for radio-frequency and microwave applications. In this work, SOI low-noise amplifiers (LNA) operating at 1.8-GHz under 1.5-V power supply are reported for the first time and the high-frequency noise characteristics are studied. A physical SOI thermal noise model is applied, and all the major noise sources associated with the transistors are modeled. SPICE simulation results of the circuit noise agree well with the measurement data. An LNA composed of floating-body SOI devices offers better performance than that with body-tied devices.

I and i

Abstract: There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality. Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

疟原虫var基因转换速率变化导致抗原变异[英]／Paul H, Robert P, Christodoulou Z, et al//Proc Natl Acad Sci U S A

Abstract: 抗原变异可使得多种致病微生物易于逃避宿主免疫应答。表达在感染红细胞表面的恶性疟原虫红细胞表面蛋白1（PfPMP1）与感染红细胞、内皮细胞、树突状细胞以及胎盘的单个或多个受体作用，在黏附及免疫逃避中起关键的作用。每个单倍体基因组var基因家族编码约60种成员，通过启动转录不同的var基因变异体为抗原变异提供了分子基础。

High-κ gate dielectrics: Current status and materials properties considerations

Abstract: Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.1 μm complementary metal–oxide–semiconductor (CMOS) technology. A systematic consideration of the required properties of gate dielectrics indicates that the key guidelines for selecting an alternative gate dielectric are (a) permittivity, band gap, and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. A review of current work and literature in the area of alternate gate dielectrics is given. Based on reported results and fundamental considerations, the pseudobinary materials systems offer large flexibility and show the most promise toward success...

Design of Analog CMOS Integrated Circuits

Abstract: The CMOS technology area has quickly grown, calling for a new text--and here it is, covering the analysis and design of CMOS integrated circuits that practicing engineers need to master to succeed. Filled with many examples and chapter-ending problems, the book not only describes the thought process behind each circuit topology, but also considers the rationale behind each modification. The analysis and design techniques focus on CMOS circuits but also apply to other IC technologies. Table of contents 1 Introduction to Analog Design 2 Basic MOS Device Physics 3 Single-Stage Amplifiers 4 Differential Amplifiers 5 Passive and Active Current Mirrors 6 Frequency Response of Amplifiers 7 Noise 8 Feedback 9 Operational Amplifiers 10 Stability and Frequency Compensation 11 Bandgap References 12 Introduction to Switched-Capacitor Circuits 13 Nonlinearity and Mismatch 14 Oscillators 15 Phase-Locked Loops 16 Short-Channel Effects and Device Models 17 CMOS Processing Technology 18 Layout and Packaging

Prospects of Colloidal Nanocrystals for Electronic and Optoelectronic Applications

Abstract: Nanocrystals (NCs) discussed in this Review are tiny crystals of metals, semiconductors, and magnetic material consisting of hundreds to a few thousand atoms each. Their size ranges from 2-3 to about 20 nm. What is special about this size regime that placed NCs among the hottest research topics of the last decades? The quantum mechanical coupling * To whom correspondence should be addressed. E-mail: dvtalapin@uchicago.edu. † The University of Chicago. ‡ Argonne National Lab. Chem. Rev. 2010, 110, 389–458 389