There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

抗原变异可使得多种致病微生物易于逃避宿主免疫应答。表达在感染红细胞表面的恶性疟原虫红细胞表面蛋白1（PfPMP1）与感染红细胞、内皮细胞、树突状细胞以及胎盘的单个或多个受体作用，在黏附及免疫逃避中起关键的作用。每个单倍体基因组var基因家族编码约60种成员，通过启动转录不同的var基因变异体为抗原变异提供了分子基础。

疟原虫var基因转换速率变化导致抗原变异[英]／Paul H, Robert P, Christodoulou Z, et al//Proc Natl Acad Sci U S A

Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.1 μm complementary metal–oxide–semiconductor (CMOS) technology. A systematic consideration of the required properties of gate dielectrics indicates that the key guidelines for selecting an alternative gate dielectric are (a) permittivity, band gap, and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. A review of current work and literature in the area of alternate gate dielectrics is given. Based on reported results and fundamental considerations, the pseudobinary materials systems offer large flexibility and show the most promise toward success...

/pdf/high-k-gate-dielectrics-current-status-and-materials-zjvba0c4u8.pdf

High-κ gate dielectrics: Current status and materials properties considerations

The CMOS technology area has quickly grown, calling for a new text--and here it is, covering the analysis and design of CMOS integrated circuits that practicing engineers need to master to succeed. Filled with many examples and chapter-ending problems, the book not only describes the thought process behind each circuit topology, but also considers the rationale behind each modification. The analysis and design techniques focus on CMOS circuits but also apply to other IC technologies.
Table of contents

1 Introduction to Analog Design
2 Basic MOS Device Physics
3 Single-Stage Amplifiers
4 Differential Amplifiers
5 Passive and Active Current Mirrors
6 Frequency Response of Amplifiers
7 Noise
8 Feedback
9 Operational Amplifiers
10 Stability and Frequency Compensation
11 Bandgap References
12 Introduction to Switched-Capacitor Circuits
13 Nonlinearity and Mismatch
14 Oscillators
15 Phase-Locked Loops
16 Short-Channel Effects and Device Models
17 CMOS Processing Technology
18 Layout and Packaging

/pdf/design-of-analog-cmos-integrated-circuits-35wxhwa3a6.pdf

Design of Analog CMOS Integrated Circuits

Nanocrystals (NCs) discussed in this Review are tiny crystals of metals, semiconductors, and magnetic material consisting of hundreds to a few thousand atoms each. Their size ranges from 2-3 to about 20 nm. What is special about this size regime that placed NCs among the hottest research topics of the last decades? The quantum mechanical coupling * To whom correspondence should be addressed. E-mail: dvtalapin@uchicago.edu. † The University of Chicago. ‡ Argonne National Lab. Chem. Rev. 2010, 110, 389–458 389

/pdf/prospects-of-colloidal-nanocrystals-for-electronic-and-3dxpyhl3r7.pdf

Prospects of Colloidal Nanocrystals for Electronic and Optoelectronic Applications

45nm node planar-SOI technology with 0.296μm2 6T-SRAM cell

— High-quality jet vapor deposition nitride is investi-gated as a tunnel dielectric for flash memory device application.Compared to control devices with SiO 2 tunnel dielectric, fasterprogramming speed as well as better retention time are achievedwith low programming voltage. The p-channel devices can be pro-grammed by hot electrons and erased by hot holes, or vice versa.Multilevel programming capability is shown.Index Terms— Charge injection, semiconductor memories, sil-icon nitride. I. I NTRODUCTION F LASH memory has the advantage of nonvolatility overDRAM, but has much slower program/erase speed andrequires higher operating voltages. In a conventional flashmemory device programmed by hot-electron injection, elec-trons must have energy close to or higher than that of the oxidebarrier (3.15 eV) to be injected into the floating gate. A verysmall percentage of electrons in the channel have such highenergy [1], so the current injected into the floating gate is verysmall, resulting in slow programming speed. High voltages arerequired to produce these hot electrons, so that it is difficult toscale the program/erase voltages with the technology node. Alow-barrier tunnel dielectric is necessary to improve program-ming efficiency and speed with the possibility of reducing theoperating voltages.Recently, jet vapor deposition (JVD) nitride has been demon-strated to be a promising high-quality gate dielectric for futureCMOS technologies [2] since it offers smaller gate-leakage cur-rent and reduced stress-induced leakage current compared toSiO gate dielectric. Due to its low barrier for electrons (2.12eV), JVD nitride can be used as the tunnel dielectric in a flashmemory device in order to enhance hot-electron injection andthereby improve the programming speed. Since the tunnelingbarrier for holes is only 1.9 eV, hot hole injection can be usedfor erasingwith appropriateoperatingvoltages.In thiswork, theperformance characteristics of the first p-channel flash memorydevices with JVD nitride tunnel dielectric are presented. Thep-channel flash memory devices offer several advantages overtheir n-channel counterparts: lower power, higher speed, and

JVD Silicon Nitride as Tunnel Dielectric in p-Channel

The flicker noise in MOSFETs with short gate lengths ( L< 1 µm) is severely degraded by the presence of a thick high-k gate dielectric layer. The gate length dependence of flicker noise becomes stronger with increasing high-k dielectric thickness—but only for n-FET. To explain these phenomena, a model based on excess traps at the gate edges has been devel- oped. This model explains the flicker-noise dependence on high-k dielectric thickness and gate length and has successfully repro- duced the experimental data. Based on the model, the impact of gate-length scaling is evaluated for future mixed-signal ICs using high-k gate-dielectric technology. The deployment of high-k gate dielectric adds another gate-length-scaling limit for analog devices due to the noise consideration. Index Terms—Analog, flicker noise (1/f noise), hafnium silicon oxynitride (HfSiON), mixed signal.

Flicker-Noise Impact on Scaling of Mixed-Signal

The viability of lead zirconate titanate (PZT) films as a storage dielectric for DRAM applications is discussed. 4000 AA PZT films with an effective SiO/sub 2/ thickness less than 17 AA were prepared by sol-gel deposition. The films exhibited ohmic behavior at low fields and exponential field dependence at high fields. The conduction characteristics can be modeled accurately using expressions derived for ionic conductivity. At the same effective SiO/sub 2/ field, the leakage and time-dependent dielectric breakdown (TDDB) characteristics are superior to other dielectric structures. However, lifetime extrapolations to worst-case operating conditions show that TDDB may be a very serious limitation for DRAM applications. Optimization of material properties of PZT films, especially the TDDB lifetime, is necessary for reliable DRAM operation. >

Electrical conduction and breakdown in sol-gel derived PZT thin films

It is shown for the first time that HfSiON gate dielectric thickness has a strong impact on the flicker (1/f) noise of devices with Lg < 1mum. We have developed a simple model for both gate length (Lg) and HfSiON thickness dependences of N-FET flicker noise, based on excess traps at the gate-edges. P-FET noise does not exhibit such strong dependences. Scaling of future analog devices with high-k gate stack may be limited by noise considerations

Chenming Hu

Papers

45nm node planar-SOI technology with 0.296μm2 6T-SRAM cell

JVD Silicon Nitride as Tunnel Dielectric in p-Channel

Flicker-Noise Impact on Scaling of Mixed-Signal

Electrical conduction and breakdown in sol-gel derived PZT thin films

Impact of HfSiON Induced Flicker Noise on Scaling of Future Mixed-Signal CMOS