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Chenming Hu
Researcher at University of California, Berkeley
Publications - 1300
Citations - 60963
Chenming Hu is an academic researcher from University of California, Berkeley. The author has contributed to research in topics: MOSFET & Gate oxide. The author has an hindex of 119, co-authored 1296 publications receiving 57264 citations. Previous affiliations of Chenming Hu include Motorola & National Chiao Tung University.
Papers
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Proceedings ArticleDOI
Process-strained Si (PSS) CMOS technology featuring 3D strain engineering
C.-H. Ge,C.-C. Lin,C.-H. Ko,C.-C. Huang,Y.-C. Huang,B.-W. Chan,B.-C. Perng,C.-C. Sheu,P.-Y. Tsai,L.-G. Yao,C.-L. Wu,T.-L. Lee,C.-J. Chen,C.-T. Wang,S.-C. Lin,Y.-C. Yeo,Chenming Hu +16 more
TL;DR: In this article, a process-strained Si (PSS) CMOS technology using the concept of three-dimensional (3D) strain engineering is presented, which includes stress engineering of trench isolation, silicide, and cap layer to improve NMOS and PMOS performance simultaneously.
Journal ArticleDOI
A new look at impact ionization-Part II: Gain and noise in short avalanche photodiodes
P. Yuan,K.A. Anselm,Chenming Hu,H. Nie,C. Lenox,Archie L. Holmes,B. G. Streetman,Joe C. Campbell,R.J. McIntyre +8 more
TL;DR: In this paper, a new theory for impact ionization that utilizes history-dependent ionization coefficients to account for the nonlocal nature of the ionization process has been described, and a systematic study of the noise characteristics of GaAs homojunction avalanche photodiodes with different multiplication layer thicknesses is also presented.
Patent
Electrically programmable memory device employing source side injection
TL;DR: In this article, an electrically programmable and eraseable memory element using source-side hot-electron injection is presented. But the authors do not specify the source and drain regions.
Journal ArticleDOI
Effects of the Variation of Ferroelectric Properties on Negative Capacitance FET Characteristics
TL;DR: In this article, the effect of the variation of ferroelectric material properties (thickness, polarization, and coercivity) on the performance of negative capacitance FETs was studied.
Proceedings ArticleDOI
On thermal effects in deep sub-micron VLSI interconnects
TL;DR: This paper presents a comprehensive analysis of the thermal effects in advanced high performance interconnect systems arising due to self-heating under various circuit conditions, including electrostatic discharge.