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Author

Chenming Hu

Other affiliations: Motorola, National Chiao Tung University, Semtech  ...read more
Bio: Chenming Hu is an academic researcher from University of California, Berkeley. The author has contributed to research in topics: MOSFET & Gate oxide. The author has an hindex of 119, co-authored 1296 publications receiving 57264 citations. Previous affiliations of Chenming Hu include Motorola & National Chiao Tung University.
Topics: MOSFET, Gate oxide, CMOS, Gate dielectric, Transistor


Papers
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Proceedings ArticleDOI
Jian Chen1, Parke1, King1, Assaderaghi1, Ko1, Chenming Hu1 
01 Jan 1992
TL;DR: In this article, a high speed Silicon-on-Insulator (SOSI) technology was developed, and a high performance circuit operating at very low power supply voltages was realized.
Abstract: A high speed Silicon-on-Insulator technology was developed, and a high performance circuit operating at very low power supply voltages was realized. The SOI MOSFETs fabricated on ultra-thin SOI film are fully-depleted and demonstrate excellent short channel behavior. At power supply voltage of V/sub DD/=1.5 V and room temperature, typical propagation delay of 18 ps/stage was obtained for depletion-mode NMOS inverter ring oscillator. The best result shows delay time of 14 ps/stage at V/sub DD/=1.5 V for ring oscillator fabricated on 500 AA SOI film with T/sub ox/=70 AA. This are the best results reported for power supply voltage of 1.5 V at room temperature. >

10 citations

Journal ArticleDOI
TL;DR: In this article, a model of polycrystalline ferroelectric (FE) capacitors is presented for simulating circuits containing FE capacitors using commercial SPICE simulators for arbitrary applied voltage waveforms.
Abstract: We present a compact model of polycrystalline ferroelectric (FE) capacitors. The polycrystalline thin-film material is modeled as a collection of independent grains or grain groups. Each grain or grain group is characterized by its local field-dependent switching rate, which is characterized by a distribution function such as Gaussian or type-2 generalized beta distribution. This computationally efficient model accurately reproduces the published experimental polarization switching waveforms and the switching current waveforms in response to all reported applied voltage waveforms. The model tracks the polarization history so that it can simulate the transition between major and minor and among minor loops as well as accumulative polarization which cannot be captured by the conventional models. This model is intended for simulating circuits containing FE capacitors using commercial SPICE simulators for arbitrary applied voltage waveforms. It also has the capability of simulating the discrete switching and device variability in small-area FE capacitors having a small number of grains, although there is no available experimental data to check the model accuracy in this regard.

10 citations

Proceedings ArticleDOI
09 Jun 1998
TL;DR: In this article, a poly-Si/sub 1-x/Ge/sub x/gated dual-gate CMOS performance is optimized at /spl sim/20% Ge content in terms of SCE and PDE.
Abstract: Scaling of CMOS technology to the deep-submicron regime has been driven by the need for higher speed and integration density, as well as lower power operation. Dual-gate technology offers several advantages, including reduced short-channel effect (SCE) by surface-channel operation of both NMOS and PMOS devices, and low and symmetrical threshold voltages required for low supply voltages. However, new problems such as the poly-gate-depletion effect (PDE) emerge as the dimensions of devices enter the deep-submicron regime. Poly-Si/sub 1-x/Ge/sub x/ has recently been reported as a promising alternative gate material. Poly-Si/sub 1-x/Ge/sub x/-gated devices with lower gate sheet resistance, higher current drive and less PDE as compared to conventional poly-Si-gated devices have been demonstrated. In this work poly-Si/sub 1-x/Ge/sub x/ dual-gate CMOS performance is demonstrated to be optimized at /spl sim/20% Ge content in terms of SCE and PDE. The use of poly-Si/sub 1-x/Ge/sub x/ gate can help to alleviate boron penetration problem without degrading gate oxide reliability.

10 citations

Proceedings ArticleDOI
10 Dec 1995
TL;DR: In this paper, the authors studied the statistical variation of NMOSFET hot-carrier lifetime and showed that the variation in lifetime among spatially separate dies is more significant than the variation within each die.
Abstract: The statistical variation of NMOSFET hot-carrier lifetime is studied. The variation in lifetime among spatially separate dies is more significant than the variation within each die. Due to the statistical nature of device hot-carrier lifetime, hot-carrier induced circuit delay degradation in critical paths is a statistical distribution rather than a deterministic parameter. A statistical hot-carrier simulator has been developed to predict the impact that statistical variation of device hot-carrier lifetime has on circuit reliability.

10 citations

Patent
Yee-Chia Yeo1, Chenming Hu
25 Jul 2003
TL;DR: In this paper, a decoupling capacitor is formed on a semiconductor substrate that includes a silicon surface layer, and a substantially flat bottom electrode is formed in a portion of the semiconductor surface layer.
Abstract: A decoupling capacitor is formed on a semiconductor substrate that includes a silicon surface layer. A substantially flat bottom electrode is formed in a portion of the semiconductor surface layer. A capacitor dielectric overlies the bottom electrode. The capacitor dielectric is formed from a high permittivity dielectric with a relative permittivity, preferably greater than about 5. The capacitor also includes a substantially flat top electrode that overlies the capacitor dielectric. In the preferred application, the top electrode is connected to a first reference voltage line and the bottom electrode is connected to a second reference voltage line.

10 citations


Cited by
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Journal ArticleDOI

[...]

08 Dec 2001-BMJ
TL;DR: There is, I think, something ethereal about i —the square root of minus one, which seems an odd beast at that time—an intruder hovering on the edge of reality.
Abstract: There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality. Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

33,785 citations

28 Jul 2005
TL;DR: PfPMP1)与感染红细胞、树突状组胞以及胎盘的单个或多个受体作用,在黏附及免疫逃避中起关键的作�ly.
Abstract: 抗原变异可使得多种致病微生物易于逃避宿主免疫应答。表达在感染红细胞表面的恶性疟原虫红细胞表面蛋白1(PfPMP1)与感染红细胞、内皮细胞、树突状细胞以及胎盘的单个或多个受体作用,在黏附及免疫逃避中起关键的作用。每个单倍体基因组var基因家族编码约60种成员,通过启动转录不同的var基因变异体为抗原变异提供了分子基础。

18,940 citations

Journal ArticleDOI
TL;DR: In this paper, a review of the literature in the area of alternate gate dielectrics is given, based on reported results and fundamental considerations, the pseudobinary materials systems offer large flexibility and show the most promise toward success.
Abstract: Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.1 μm complementary metal–oxide–semiconductor (CMOS) technology. A systematic consideration of the required properties of gate dielectrics indicates that the key guidelines for selecting an alternative gate dielectric are (a) permittivity, band gap, and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. A review of current work and literature in the area of alternate gate dielectrics is given. Based on reported results and fundamental considerations, the pseudobinary materials systems offer large flexibility and show the most promise toward success...

5,711 citations

Book
01 Jan 1999
TL;DR: The analysis and design techniques of CMOS integrated circuits that practicing engineers need to master to succeed can be found in this article, where the authors describe the thought process behind each circuit topology, but also consider the rationale behind each modification.
Abstract: The CMOS technology area has quickly grown, calling for a new text--and here it is, covering the analysis and design of CMOS integrated circuits that practicing engineers need to master to succeed. Filled with many examples and chapter-ending problems, the book not only describes the thought process behind each circuit topology, but also considers the rationale behind each modification. The analysis and design techniques focus on CMOS circuits but also apply to other IC technologies. Table of contents 1 Introduction to Analog Design 2 Basic MOS Device Physics 3 Single-Stage Amplifiers 4 Differential Amplifiers 5 Passive and Active Current Mirrors 6 Frequency Response of Amplifiers 7 Noise 8 Feedback 9 Operational Amplifiers 10 Stability and Frequency Compensation 11 Bandgap References 12 Introduction to Switched-Capacitor Circuits 13 Nonlinearity and Mismatch 14 Oscillators 15 Phase-Locked Loops 16 Short-Channel Effects and Device Models 17 CMOS Processing Technology 18 Layout and Packaging

4,826 citations

Journal ArticleDOI
TL;DR: Nanocrystals (NCs) discussed in this Review are tiny crystals of metals, semiconductors, and magnetic material consisting of hundreds to a few thousand atoms each that are among the hottest research topics of the last decades.
Abstract: Nanocrystals (NCs) discussed in this Review are tiny crystals of metals, semiconductors, and magnetic material consisting of hundreds to a few thousand atoms each. Their size ranges from 2-3 to about 20 nm. What is special about this size regime that placed NCs among the hottest research topics of the last decades? The quantum mechanical coupling * To whom correspondence should be addressed. E-mail: dvtalapin@uchicago.edu. † The University of Chicago. ‡ Argonne National Lab. Chem. Rev. 2010, 110, 389–458 389

3,720 citations