Chenming Hu

Bio: Chenming Hu is an academic researcher from University of California, Berkeley. The author has contributed to research in topics: MOSFET & Gate oxide. The author has an hindex of 119, co-authored 1296 publications receiving 57264 citations. Previous affiliations of Chenming Hu include Motorola & National Chiao Tung University.

Bias polarity dependent effects of P+floating gate EEPROMs

Abstract: EEPROM devices with either N-type or P-type floating gate were fabricated and characterized. Program/erase speeds and stress-induced leakage current-related retention characteristics for both types of devices are explained. Discrepancies between previously published reports on P-type floating gate devices and PMOS gate current measurements are resolved. The feasibility of integrating P-type floating gate EEPROMs in high density memory arrays is examined.

Bsim3v3 mosfet model

Abstract: The BSIM3v3 compact MOSFET model is reviewed. It is a physics-based model that is accurate, smooth, continuous, scalable, predictive and computationally robust over different regions of operation and a wide geometry range. BSIM3v3 considers all major physical effects in deep submicron MOSFETs, making it a good base for future sub-0.1m device models and for statistical circuit designs. A key feature of the model lies in its thorough, accurate and functional mathematical representation of MOS device physics, which has made BSIM3v3 selected by an international consortium of semiconductor companies as the first industry standard MOSFET model.

Punchthrough transient voltage suppressor for EOS/ESD protection of low-voltage IC's

Abstract: A silicon transient voltage suppresser (TVS) is presented for off-chip EOS/ESD protection of ICs with supply voltages ranging from 3.3 V down to 1.5 V. The np/sup +/p/sup -/n four-layer TVS operates in punchthrough mode instead of the avalanche mode as in conventional TVS diodes. Performance was investigated by device simulator TMA-MEDICI for several device structure options for ultra-low-voltage EOS/ESD protection.

Thermal analysis of the fusion limits of metal interconnect under short duration current pulses

Abstract: Thermal analysis of the fusion limits of the IC metal under short duration current pulses has been performed using a quadruple level TiN/AlCu/TiN metallization system. A finite element (FE) simulation program has been calibrated to analyze the thermal effects in detail. The program can be used to predict self heating under DC and transient current conditions for various metal levels, geometries and current loading conditions. It is shown both experimentally and using FE simulations that the metal temperatures rise past 1000/spl deg/C before open circuit failure under short duration current pulses. The critical failure current is strongly influenced by the metal thickness, thermal capacity and pulse width. Further, it is shown that the ratio of the critical energy causing open circuit conditions (fusion limit), to the theoretical melt energy increases with scaling. As a result, narrower metal lines can sustain higher current densities before failure.

High V th enhancement mode GaN power devices with high I D, max using hybrid ferroelectric charge trap gate stack

Abstract: In this work, we demonstrate a new concept for realizing high threshold voltage (V th ) E-mode GaN power devices with high maximum drain current (I D, max ). A gate stack ferroelectric blocking film with charge trap layer, achieved a large positive shift of V th . The E-mode GaN MIS-HEMTs with high V th of 6 V shows I D, max 720 mA/mm. The breakdown voltage is above 1100 V.

I and i

Abstract: There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality. Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

疟原虫var基因转换速率变化导致抗原变异[英]／Paul H, Robert P, Christodoulou Z, et al//Proc Natl Acad Sci U S A

Abstract: 抗原变异可使得多种致病微生物易于逃避宿主免疫应答。表达在感染红细胞表面的恶性疟原虫红细胞表面蛋白1（PfPMP1）与感染红细胞、内皮细胞、树突状细胞以及胎盘的单个或多个受体作用，在黏附及免疫逃避中起关键的作用。每个单倍体基因组var基因家族编码约60种成员，通过启动转录不同的var基因变异体为抗原变异提供了分子基础。

High-κ gate dielectrics: Current status and materials properties considerations

Abstract: Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.1 μm complementary metal–oxide–semiconductor (CMOS) technology. A systematic consideration of the required properties of gate dielectrics indicates that the key guidelines for selecting an alternative gate dielectric are (a) permittivity, band gap, and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. A review of current work and literature in the area of alternate gate dielectrics is given. Based on reported results and fundamental considerations, the pseudobinary materials systems offer large flexibility and show the most promise toward success...

Design of Analog CMOS Integrated Circuits

Abstract: The CMOS technology area has quickly grown, calling for a new text--and here it is, covering the analysis and design of CMOS integrated circuits that practicing engineers need to master to succeed. Filled with many examples and chapter-ending problems, the book not only describes the thought process behind each circuit topology, but also considers the rationale behind each modification. The analysis and design techniques focus on CMOS circuits but also apply to other IC technologies. Table of contents 1 Introduction to Analog Design 2 Basic MOS Device Physics 3 Single-Stage Amplifiers 4 Differential Amplifiers 5 Passive and Active Current Mirrors 6 Frequency Response of Amplifiers 7 Noise 8 Feedback 9 Operational Amplifiers 10 Stability and Frequency Compensation 11 Bandgap References 12 Introduction to Switched-Capacitor Circuits 13 Nonlinearity and Mismatch 14 Oscillators 15 Phase-Locked Loops 16 Short-Channel Effects and Device Models 17 CMOS Processing Technology 18 Layout and Packaging

Prospects of Colloidal Nanocrystals for Electronic and Optoelectronic Applications

Abstract: Nanocrystals (NCs) discussed in this Review are tiny crystals of metals, semiconductors, and magnetic material consisting of hundreds to a few thousand atoms each. Their size ranges from 2-3 to about 20 nm. What is special about this size regime that placed NCs among the hottest research topics of the last decades? The quantum mechanical coupling * To whom correspondence should be addressed. E-mail: dvtalapin@uchicago.edu. † The University of Chicago. ‡ Argonne National Lab. Chem. Rev. 2010, 110, 389–458 389