Chenming Hu

Bio: Chenming Hu is an academic researcher from University of California, Berkeley. The author has contributed to research in topics: MOSFET & Gate oxide. The author has an hindex of 119, co-authored 1296 publications receiving 57264 citations. Previous affiliations of Chenming Hu include Motorola & National Chiao Tung University.

A Compact Quantum-Mechanical Model for Double-Gate MOSFET

Abstract: A bias-dependent QM correction for surface potential calculation is derived for DG MOSFETs. The QM-corrected surface potential agrees with the 2D simulation results well. This indicates that both Vth shift in the subthreshold and strong inversion regions and gate capacitance degradation in the strong inversion region due to QM are predicted simultaneously. The model can predict the complicated QM effect dependence on various device parameters, such as Nbody, Tsi, Tox, etc

Evaluation of the BSIM6 compact MOSFET model's scalability in 40nm CMOS technology

Abstract: The aggressive downscaling of advanced bulk CMOS technologies demands MOSFET models that are able to describe accurately the behavior of devices accounting for all the physical phenomena. A reliable model should have the ability to handle all the different operating regions of the MOS transistor in the whole geometry range of one technology. Targeting to meet the aforementioned needs, the new charge-based compact model BSIM6 has been developed. In this article, as a first benchmarking of BSIM6, the model is evaluated for its scaling capabilities when a single set of parameters is used. The model is compared against a state-of-the-art 40nm CMOS technology. The results attest the model's scalability under all bias conditions, proving its reliability for nowadays complex IC designs.

Modeling of high voltage LDMOSFET using industry standard BSIM6 MOS model

Abstract: In this paper we have shown the modeling of Lateral Double-Diffused MOS (LDMOS) transistor. A LDMOS structure can be divided into two parts, intrinsic channel and extended drift region. The intinsic channel region is modeled by industry standard BSIM6 model and extended drift region has been modeled by the modified CMC standard model of R3. The R3 model of non-linear resistor, which includes physical effects like velocity-saturation, self-heating etc. has been modified to include gate bias dependency. The new model has been validated with technology computer-aided design (TCAD) simulations and measured data from ON Semiconductor. The model (which is the combination of BSIM6 and R3 models) shows excellent agreement with the TCAD simulations and measured data.

Fabrication of microstructures for studies of electromigration in sub‐0.25 μm metal interconnections

Abstract: Electromigration test structures consisting of 0.1–0.5‐μm‐wide and 0.25‐μm‐thick Al(4%Cu) wires and W contacts have been fabricated on 70‐nm‐thick Si3N4 membranes using electron‐beam lithography and reactive‐ion etching. Observation of grain structure evolution with electromigration in these wires by transmission electron microscopy is reported. It is shown that dissolution of Al2Cu grains is accompanied by the growth in neighboring Al grains.

Plasma-etching induced damage in thin oxide

Abstract: It is pointed out that plasma Al etching and resist ashing processes cause Fowler-Nordheim current to flow through the oxide and that plasma-induced damage can be simulated and modeled as damage produced by constant current electrical stress. The current produced by the plasma process increases with the antenna size of the device structure. C-V measurement is a more sensitive technique for characterizing plasma-etching-induced damage than oxide breakdown. The stress current is collected only through the aluminum surfaces not covered by the photoresist during plasma processes. The plasma stress current is proportional to Al pad peripheral length during Al etching and Al pad area during photoresist stripping. A model of oxide damage due to plasma etching is proposed. >

I and i

Abstract: There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality. Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

疟原虫var基因转换速率变化导致抗原变异[英]／Paul H, Robert P, Christodoulou Z, et al//Proc Natl Acad Sci U S A

Abstract: 抗原变异可使得多种致病微生物易于逃避宿主免疫应答。表达在感染红细胞表面的恶性疟原虫红细胞表面蛋白1（PfPMP1）与感染红细胞、内皮细胞、树突状细胞以及胎盘的单个或多个受体作用，在黏附及免疫逃避中起关键的作用。每个单倍体基因组var基因家族编码约60种成员，通过启动转录不同的var基因变异体为抗原变异提供了分子基础。

High-κ gate dielectrics: Current status and materials properties considerations

Abstract: Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.1 μm complementary metal–oxide–semiconductor (CMOS) technology. A systematic consideration of the required properties of gate dielectrics indicates that the key guidelines for selecting an alternative gate dielectric are (a) permittivity, band gap, and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. A review of current work and literature in the area of alternate gate dielectrics is given. Based on reported results and fundamental considerations, the pseudobinary materials systems offer large flexibility and show the most promise toward success...

Design of Analog CMOS Integrated Circuits

Abstract: The CMOS technology area has quickly grown, calling for a new text--and here it is, covering the analysis and design of CMOS integrated circuits that practicing engineers need to master to succeed. Filled with many examples and chapter-ending problems, the book not only describes the thought process behind each circuit topology, but also considers the rationale behind each modification. The analysis and design techniques focus on CMOS circuits but also apply to other IC technologies. Table of contents 1 Introduction to Analog Design 2 Basic MOS Device Physics 3 Single-Stage Amplifiers 4 Differential Amplifiers 5 Passive and Active Current Mirrors 6 Frequency Response of Amplifiers 7 Noise 8 Feedback 9 Operational Amplifiers 10 Stability and Frequency Compensation 11 Bandgap References 12 Introduction to Switched-Capacitor Circuits 13 Nonlinearity and Mismatch 14 Oscillators 15 Phase-Locked Loops 16 Short-Channel Effects and Device Models 17 CMOS Processing Technology 18 Layout and Packaging

Prospects of Colloidal Nanocrystals for Electronic and Optoelectronic Applications

Abstract: Nanocrystals (NCs) discussed in this Review are tiny crystals of metals, semiconductors, and magnetic material consisting of hundreds to a few thousand atoms each. Their size ranges from 2-3 to about 20 nm. What is special about this size regime that placed NCs among the hottest research topics of the last decades? The quantum mechanical coupling * To whom correspondence should be addressed. E-mail: dvtalapin@uchicago.edu. † The University of Chicago. ‡ Argonne National Lab. Chem. Rev. 2010, 110, 389–458 389