Chenming Hu

Bio: Chenming Hu is an academic researcher from University of California, Berkeley. The author has contributed to research in topics: MOSFET & Gate oxide. The author has an hindex of 119, co-authored 1296 publications receiving 57264 citations. Previous affiliations of Chenming Hu include Motorola & National Chiao Tung University.

Characterization of hot-carrier effects in thin-film fully-depleted SOI MOSFETs

Abstract: Previous conflicting reports concerning fully-depleted SOI device hot electron reliability is partially due to misunderstanding over the maximum channel electric field (E/sub m/). Experimental results using SOI MOSFETs with body contacts indicate that E/sub m/ is just a weak function of thin-film SOI thickness (T/sub si/) and E/sub m/ can be significantly lower than in a bulk device with drain junction depth (X/sub j/) comparable to T/sub si/ The theoretical correlation between SOI MOSFET's gate current and substrate current are experimentally confirmed. This provides a means (I/sub G/) of studying E, in SOI device without body contacts. Both N- and P-MOSFETs can have better hot-carrier reliability than comparable bulk devices. Thin film SOI MOSFETs have better prospects for meeting breakdown voltage and hot-electron reliability requirements than previously thought. >

Bipolar transistor degradation under dynamic hot carrier stress

Abstract: Hot carrier induced bipolar transistor degradation under dynamic stress is studied. The model, ΔIB ∝ (IR1.8 t)0.5, established from d.c. emitter-base reverse bias stress measurements is found to be still valid under pulse stress down to 20 ns pulse width, where ΔIB is drift of base current, IR is reverse emitter-base current under stress and t is stress time. Although partial degradation recovery is observed under d.c. emitter-base forward bias, ΔIB from alternating reverse-forward stress representative BiCMOS circuit operation agrees with the ΔIB model with no significant recovery effect. This is explained by a higher degradation rate after recovery of previous damage. An experimental basis of BiCMOS circuit reliability testing simulation is thus provided.

Study of Inherent Gate Coupling Nonuniformity of InAs/GaSb Vertical TFETs

Abstract: An electrostatic nonuniformity in the cantilever vertical tunneling FETs intrinsically exists in the InAs/GaSb junction to InAs cantilever transition region. The effects of the coupling ratio (CR) nonuniformity are investigated in this paper. The results show that the switching characteristics are degraded by the CR nonuniformity, especially in the case of large InAs/GaSb band offset. This paper also reveals that the nonuniformity in InAs/GaSb vertical tunneling FETs can be mitigated with the optimized band offset of heterojunction, scaling of oxide thickness, and acute angle etching profile.

Reliability of Ferroelectric HfO 2 -based Memories: From MOS Capacitor to FeFET

Abstract: Ferroelectric (FE) FETs as nonvolatile memories have enjoyed a recent resurgence among emerging memory technologies due to the discovery of ferroelectricity in HfO 2 [1] . FE-HfO 2 offers attractive qualities such as CMOS compatibility, fast read/write speed, excellent retention, and scalability [2] . However, as write endurance remains a concern, various techniques have been proposed to improve endurance; among them, popular ones include engineering of the interfacial layer (IL), modulating the FE oxide properties, and changing the gate electrode [ 2 - 5 ]. In this work, we demonstrate for the first time a systematic, reliable, and rapid method to qualitatively predict the FE endurance of prospective gate stack designs prior to running a full FeFET fabrication process. MOSCAPs incorporating FE gate stacks (∼ 4.5 nm) realized via a one-step lithography process on highly doped Si are compared against real endurance results from SOI FeFETs incorporating the same FE oxides. The FeFETs demonstrated in this work boast impressive programmability (0.4 - 0.5V memory window at ±3.3V, 1 µ s) and a strong potential for further scalability.

Optimization of sub-5-nm multiple-thickness gate oxide formed by oxygen implantation

Abstract: A new method of growing multiple gate oxide thicknesses below 5 nm using masked oxygen implantation is presented. Multiple thicknesses can be achieved on the same wafer without degradation in the oxide properties. The oxygen implanted oxide quality is comparable to that of thermally grown oxides. Moreover, the effects of oxygen implant damage is minimized with higher implant energies, thicker sacrificial oxides, and low-temperature annealing.

I and i

Abstract: There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality. Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

疟原虫var基因转换速率变化导致抗原变异[英]／Paul H, Robert P, Christodoulou Z, et al//Proc Natl Acad Sci U S A

Abstract: 抗原变异可使得多种致病微生物易于逃避宿主免疫应答。表达在感染红细胞表面的恶性疟原虫红细胞表面蛋白1（PfPMP1）与感染红细胞、内皮细胞、树突状细胞以及胎盘的单个或多个受体作用，在黏附及免疫逃避中起关键的作用。每个单倍体基因组var基因家族编码约60种成员，通过启动转录不同的var基因变异体为抗原变异提供了分子基础。

High-κ gate dielectrics: Current status and materials properties considerations

Abstract: Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.1 μm complementary metal–oxide–semiconductor (CMOS) technology. A systematic consideration of the required properties of gate dielectrics indicates that the key guidelines for selecting an alternative gate dielectric are (a) permittivity, band gap, and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. A review of current work and literature in the area of alternate gate dielectrics is given. Based on reported results and fundamental considerations, the pseudobinary materials systems offer large flexibility and show the most promise toward success...

Design of Analog CMOS Integrated Circuits

Abstract: The CMOS technology area has quickly grown, calling for a new text--and here it is, covering the analysis and design of CMOS integrated circuits that practicing engineers need to master to succeed. Filled with many examples and chapter-ending problems, the book not only describes the thought process behind each circuit topology, but also considers the rationale behind each modification. The analysis and design techniques focus on CMOS circuits but also apply to other IC technologies. Table of contents 1 Introduction to Analog Design 2 Basic MOS Device Physics 3 Single-Stage Amplifiers 4 Differential Amplifiers 5 Passive and Active Current Mirrors 6 Frequency Response of Amplifiers 7 Noise 8 Feedback 9 Operational Amplifiers 10 Stability and Frequency Compensation 11 Bandgap References 12 Introduction to Switched-Capacitor Circuits 13 Nonlinearity and Mismatch 14 Oscillators 15 Phase-Locked Loops 16 Short-Channel Effects and Device Models 17 CMOS Processing Technology 18 Layout and Packaging

Prospects of Colloidal Nanocrystals for Electronic and Optoelectronic Applications

Abstract: Nanocrystals (NCs) discussed in this Review are tiny crystals of metals, semiconductors, and magnetic material consisting of hundreds to a few thousand atoms each. Their size ranges from 2-3 to about 20 nm. What is special about this size regime that placed NCs among the hottest research topics of the last decades? The quantum mechanical coupling * To whom correspondence should be addressed. E-mail: dvtalapin@uchicago.edu. † The University of Chicago. ‡ Argonne National Lab. Chem. Rev. 2010, 110, 389–458 389