Chenming Hu

Bio: Chenming Hu is an academic researcher from University of California, Berkeley. The author has contributed to research in topics: MOSFET & Gate oxide. The author has an hindex of 119, co-authored 1296 publications receiving 57264 citations. Previous affiliations of Chenming Hu include Motorola & National Chiao Tung University.

Interface quality of SOI MOSFET's reflected in noise and mobility

Abstract: The trap density of both front and back interfaces of SOI (silicon-on-insulator) devices is estimated using low frequency noise measurement. The authors present the complete set of effective mobilities for both n- and p-channel SOI MOSFETs at both the front and back channels and relate them to the trap densities. It is found that the interface qualities of the front and back sides are similar in SIMOX (separation by implanted oxygen) SOI MOSFETs from the noise and mobility standpoint. The very low field effective mobility of SOI NMOS is lower than that of bulk NMOS due to increased interface trap densities for SOI devices and the effective mobility of the edge transistor is lower. >

Compact models for real device effects in FinFETs: Quantum-mechanical confinement and double junctions in FinFETs

Abstract: A novel geometrically scalable, phenomenological model for quantum mechanical carrier charge centroid in thin fins is presented. A model for capturing the capacitance characteristics of a graded double-junction arising out of punchthrough stop implant in bulk-FinFETs is also proposed. Developed models have been included in BSIM-CMG multi-gate transistor compact model.

A Unified Flicker Noise Model for FDSOI MOSFETs Including Back-bias Effect

Abstract: A physics-based unified flicker noise model for FDSOI transistor is proposed. Flicker noise power spectral density (PSD) at the front and back interfaces are calculated using oxide-trap-induced carrier number (CNF) and correlated surface mobility fluctuation (CMF) mechanisms. The model predicts correct flicker noise behavior from weak inversion region to strong inversion region for a wide range of the front and backgate voltages. The proposed model is computationally efficient and implementable in any SPICE model for circuit simulations.

Copper wiring with high temperature superconductor (HTS) layer

Abstract: Semiconductor devices and methods of forming the semiconductor devices using an HTS (High Temperature Superconductor) layer in combination with a typical diffusion layer between the dielectric material and the copper (or other metal) conductive wiring. The HTS layer includes a superconductor material comprised of barium copper oxide and a rare earth element. The rare earth element yttrium is particularly suitable. For semiconductor devices having other semiconductor circuits or elements above the wiring, a capping layer of HTS material is deposited over the wiring before a cover layer of dielectric is deposited.

Characterizing a single hot-electron-induced trap in submicron MOSFET using random telegraph noise

Abstract: Individual interface traps generated by hot-electron stress were observed for the first time. Single trap filling and emptying can cause 0.1% step noise in drain current due to coulombic scattering. Trap location (3-10 A from interface), time constant, energy and escape frequency are found to be very different from pre-stress (process-induced) traps. Random telegraph (RTS) noise was found to be a useful tool for studying stress-induced interface traps. It is more easily observable for stress-induced traps than process-induced traps due to the small stress area and low stress-induced trap density after light stressing. Using RTS as a characterization tool, it was found that the stress-induced traps are located closer to the interface, and therefore have a shorter time constant and much stronger influence on scattering and DId than process-induced traps. RTS only reveals those traps near the Fermi level, while the DC MOSFET IV degradation is also influenced by all the charged traps

I and i

Abstract: There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality. Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

疟原虫var基因转换速率变化导致抗原变异[英]／Paul H, Robert P, Christodoulou Z, et al//Proc Natl Acad Sci U S A

Abstract: 抗原变异可使得多种致病微生物易于逃避宿主免疫应答。表达在感染红细胞表面的恶性疟原虫红细胞表面蛋白1（PfPMP1）与感染红细胞、内皮细胞、树突状细胞以及胎盘的单个或多个受体作用，在黏附及免疫逃避中起关键的作用。每个单倍体基因组var基因家族编码约60种成员，通过启动转录不同的var基因变异体为抗原变异提供了分子基础。

High-κ gate dielectrics: Current status and materials properties considerations

Abstract: Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.1 μm complementary metal–oxide–semiconductor (CMOS) technology. A systematic consideration of the required properties of gate dielectrics indicates that the key guidelines for selecting an alternative gate dielectric are (a) permittivity, band gap, and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. A review of current work and literature in the area of alternate gate dielectrics is given. Based on reported results and fundamental considerations, the pseudobinary materials systems offer large flexibility and show the most promise toward success...

Design of Analog CMOS Integrated Circuits

Abstract: The CMOS technology area has quickly grown, calling for a new text--and here it is, covering the analysis and design of CMOS integrated circuits that practicing engineers need to master to succeed. Filled with many examples and chapter-ending problems, the book not only describes the thought process behind each circuit topology, but also considers the rationale behind each modification. The analysis and design techniques focus on CMOS circuits but also apply to other IC technologies. Table of contents 1 Introduction to Analog Design 2 Basic MOS Device Physics 3 Single-Stage Amplifiers 4 Differential Amplifiers 5 Passive and Active Current Mirrors 6 Frequency Response of Amplifiers 7 Noise 8 Feedback 9 Operational Amplifiers 10 Stability and Frequency Compensation 11 Bandgap References 12 Introduction to Switched-Capacitor Circuits 13 Nonlinearity and Mismatch 14 Oscillators 15 Phase-Locked Loops 16 Short-Channel Effects and Device Models 17 CMOS Processing Technology 18 Layout and Packaging

Prospects of Colloidal Nanocrystals for Electronic and Optoelectronic Applications

Abstract: Nanocrystals (NCs) discussed in this Review are tiny crystals of metals, semiconductors, and magnetic material consisting of hundreds to a few thousand atoms each. Their size ranges from 2-3 to about 20 nm. What is special about this size regime that placed NCs among the hottest research topics of the last decades? The quantum mechanical coupling * To whom correspondence should be addressed. E-mail: dvtalapin@uchicago.edu. † The University of Chicago. ‡ Argonne National Lab. Chem. Rev. 2010, 110, 389–458 389