C
Chenming Hu
Researcher at University of California, Berkeley
Publications - 1300
Citations - 60963
Chenming Hu is an academic researcher from University of California, Berkeley. The author has contributed to research in topics: MOSFET & Gate oxide. The author has an hindex of 119, co-authored 1296 publications receiving 57264 citations. Previous affiliations of Chenming Hu include Motorola & National Chiao Tung University.
Papers
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Journal ArticleDOI
Temperature acceleration of time-dependent dielectric breakdown
TL;DR: In this paper, a model for predicting the temperature dependence of time-to-breakdown t/sub BD/ in MOS circuits was proposed, and the activation energy was found to increase with the breakdown time.
Proceedings ArticleDOI
Ultra-thin silicon dioxide leakage current and scaling limit
TL;DR: In this article, the authors make modifications to Fowler-Nordheim tunneling current analysis to model accurately the measured conduction characteristics of insulator layers thinner than 6 nm, and the most significant is direct tunneling for which a closed-form expression is introduced.
Journal ArticleDOI
Dual-metal gate CMOS technology with ultrathin silicon nitride gate dielectric
Yee-Chia Yeo,Qiang Lu,Pushkar Ranade,Hideki Takeuchi,Kevin Yang,I. Polishchuk,Tsu-Jae King,Chenming Hu,S.C. Song,H.F. Luan,Dim-Lee Kwong +10 more
TL;DR: In this article, a dual-metal gate complementary metal oxide semiconductor (CMOS) technology using titanium (Ti) and molybdenum (Mo) as the gate electrodes for the N-metal oxide field effect transistors (N-MOSFETs) was presented.
Journal ArticleDOI
A 0.1-/spl mu/m delta-doped MOSFET fabricated with post-low-energy implanting selective epitaxy
TL;DR: In this paper, a simple fabrication technology for delta-doped MOSFETs, named post-low-energy implanting selective epitaxy (PLISE), was presented, which needs no additional photo-lithography mask, deposition step or etching step even for CMOS devices.
Journal ArticleDOI
Analysis and Compact Modeling of Negative Capacitance Transistor with High ON-Current and Negative Output Differential Resistance—Part I: Model Description
Girish Pahwa,Tapas Dutta,Amit Agarwal,Sourabh Khandelwal,Sayeef Salahuddin,Chenming Hu,Yogesh Singh Chauhan +6 more
TL;DR: An accurate and computationally efficient physics-based compact model to quantitatively analyze negative capacitance FET (NCFET) for real circuit design applications and accurately captures different aspects of NCFET is presented.