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Chenming Hu

Researcher at University of California, Berkeley

Publications -  1300
Citations -  60963

Chenming Hu is an academic researcher from University of California, Berkeley. The author has contributed to research in topics: MOSFET & Gate oxide. The author has an hindex of 119, co-authored 1296 publications receiving 57264 citations. Previous affiliations of Chenming Hu include Motorola & National Chiao Tung University.

Papers
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Patent

Semiconductor-on-insulator SRAM configured using partially-depleted and fully-depleted transistors

TL;DR: In this article, a static memory element includes a first inverter having an input coupled to a left bit node and an output coupled to the right bit node, and a second inverter has an input coupling to the left right bit nodes.
Patent

Multiple-gate transistors with improved gate control

TL;DR: In this article, a method for fabricating a multiple-gate device including the steps of providing a substrate of a semi-conducting layer on an insulator stack, patterning a semiconductor fin, etching the insulator layer at the base of the fin forming an undercut, depositing a gate dielectric layer overlying the fin, and depositing an electrically conductive layer over the gate dieelectric layer, forming a gate straddling across the two sidewall surfaces and the top surface of a fin; and forming a source region and a drain region
Patent

Methods and structures for planar and multiple-gate transistors formed on SOI

TL;DR: A semiconductor device includes an insulator, a semiconductor layer, a first transistor, and a second transistor as mentioned in this paper, which is overlying the insulator layer, and the second transistor is larger than the first thickness.
Journal ArticleDOI

Hot-carrier effects in thin-film fully depleted SOI MOSFET's

TL;DR: In this paper, the theoretical correlation between SOI MOSFET's gate current and substrate current was investigated and shown to be a weak function of thin-film SOI thickness.
Journal ArticleDOI

A charge sheet capacitance model of short channel MOSFETs for SPICE

TL;DR: An analytic charge sheet capacitance model for short-channel MOSFETs is derived and implemented in SPICE based on a surface potential formulation which computes the approximate surface potential without iterations.