Chenming Hu

Bio: Chenming Hu is an academic researcher from University of California, Berkeley. The author has contributed to research in topics: MOSFET & Gate oxide. The author has an hindex of 119, co-authored 1296 publications receiving 57264 citations. Previous affiliations of Chenming Hu include Motorola & National Chiao Tung University.

High current effects in silicide films for sub-0.25 /spl mu/m VLSI technologies

Abstract: Characterization and modeling of high current conduction in TiSi/sub 2/ and CoSi/sub 2/ films formed on n/sup +/-Si and n/sup +/ poly-Si under DC and pulsed stress conditions is reported for the first time. High current conductance of silicides is shown to be strongly affected by the technology and process conditions. The nonlinear I-V characteristics of silicide films under DC and pulsed high current stress has been modeled and the nonlinearity has been shown to be due to self-heating. Two physical parameters, B and /spl lambda/, associated with DC and pulsed current stress, have been shown to be able to describe the sensitivity of the films to high current conduction. At high currents, an abrupt lowering of the resistance of the silicided structures is observed. Detailed analysis of the evolution of this resistance drop has been made. It is shown that the cause is related to the melting of the structures, which also causes degradation in the post-stress silicide film resistance. The critical current for these failures has been shown to be strongly influenced by the silicide film width and the time duration of the pulse. CoSi/sub 2/ films and films on poly-Si are shown to be more sensitive to high current conduction and degradation.

Metal gate work function adjustment for future CMOS technology

Abstract: CMOS transistors were fabricated using a single metal, [110]-Mo, as the gate material [110]-Mo shows a high work function value that is suitable for PMOSFETs, and, with nitrogen implantation, its work function can be reduced to meet the requirements of NMOSFETs The change in Mo work function can be controlled by the nitrogen implant parameters, which is potentially useful for multiple-V/sub T/ technology TEM and EDS analysis show that Mo gate electrodes are stable after undergoing a conventional CMOS process

Device challenges and opportunities

Abstract: CMOS technology is facing exciting opportunities and formidable challenges. They include mobility scaling to overcome the speed/power barrier, new gate-stack materials and/or new device structures; to overcome the gate-length/leakage barrier; nonvolatile memory and universal memory to enlarge the market, and containment of costs. CMOS has much more to give in the next two decades, yet it is not too early, especially in universities, to start searching for not-CMOS-like circuit/system architectures that may require non-existing new devices but offer the promise of dramatic reduction in power and cost.

Design in hot-carrier reliability for high performance logic applications

Abstract: Static (DC) and dynamic (AC) hot carrier degradation mechanisms were reviewed. Circuit performance degradation has been correlated to individual NMOS or PMOS device under DC stress. AC degradation model calibration and evaluation guidelines were also reviewed to ensure the use of hot-carrier reliability simulation tools at circuit level. As an example, thousand-hour inverter ring oscillator speed degradation data with different fanout, stress voltages, channel length, and processes are compared with that obtained from reliability simulation. The results show that reliability simulation is a powerful tool for logic circuit design optimization. It can predict the long-term circuit hot-carrier degradation accurately. The reliability of inverter, NAND, and NOR structures are also simulated and compared.

Electromigration interconnect lifetime under AC and pulse DC stress

Abstract: A vacancy relaxation model which predicts the DC lifetime, pulse DC lifetime, and AC lifetime for all waveforms and all frequencies above 10 kHz is proposed. The AC lifetimes of aluminum interconnect are experimentally found to be more than 10/sup 3/ times larger than DC lifetime at the same current density. AC stress lifetimes have the same dependences on current magnitude and temperature, for T >

I and i

Abstract: There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality. Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

疟原虫var基因转换速率变化导致抗原变异[英]／Paul H, Robert P, Christodoulou Z, et al//Proc Natl Acad Sci U S A

Abstract: 抗原变异可使得多种致病微生物易于逃避宿主免疫应答。表达在感染红细胞表面的恶性疟原虫红细胞表面蛋白1（PfPMP1）与感染红细胞、内皮细胞、树突状细胞以及胎盘的单个或多个受体作用，在黏附及免疫逃避中起关键的作用。每个单倍体基因组var基因家族编码约60种成员，通过启动转录不同的var基因变异体为抗原变异提供了分子基础。

High-κ gate dielectrics: Current status and materials properties considerations

Abstract: Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.1 μm complementary metal–oxide–semiconductor (CMOS) technology. A systematic consideration of the required properties of gate dielectrics indicates that the key guidelines for selecting an alternative gate dielectric are (a) permittivity, band gap, and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. A review of current work and literature in the area of alternate gate dielectrics is given. Based on reported results and fundamental considerations, the pseudobinary materials systems offer large flexibility and show the most promise toward success...

Design of Analog CMOS Integrated Circuits

Abstract: The CMOS technology area has quickly grown, calling for a new text--and here it is, covering the analysis and design of CMOS integrated circuits that practicing engineers need to master to succeed. Filled with many examples and chapter-ending problems, the book not only describes the thought process behind each circuit topology, but also considers the rationale behind each modification. The analysis and design techniques focus on CMOS circuits but also apply to other IC technologies. Table of contents 1 Introduction to Analog Design 2 Basic MOS Device Physics 3 Single-Stage Amplifiers 4 Differential Amplifiers 5 Passive and Active Current Mirrors 6 Frequency Response of Amplifiers 7 Noise 8 Feedback 9 Operational Amplifiers 10 Stability and Frequency Compensation 11 Bandgap References 12 Introduction to Switched-Capacitor Circuits 13 Nonlinearity and Mismatch 14 Oscillators 15 Phase-Locked Loops 16 Short-Channel Effects and Device Models 17 CMOS Processing Technology 18 Layout and Packaging

Prospects of Colloidal Nanocrystals for Electronic and Optoelectronic Applications

Abstract: Nanocrystals (NCs) discussed in this Review are tiny crystals of metals, semiconductors, and magnetic material consisting of hundreds to a few thousand atoms each. Their size ranges from 2-3 to about 20 nm. What is special about this size regime that placed NCs among the hottest research topics of the last decades? The quantum mechanical coupling * To whom correspondence should be addressed. E-mail: dvtalapin@uchicago.edu. † The University of Chicago. ‡ Argonne National Lab. Chem. Rev. 2010, 110, 389–458 389