Chenming Hu

Bio: Chenming Hu is an academic researcher from University of California, Berkeley. The author has contributed to research in topics: MOSFET & Gate oxide. The author has an hindex of 119, co-authored 1296 publications receiving 57264 citations. Previous affiliations of Chenming Hu include Motorola & National Chiao Tung University.

High performance cmos devices and methods for making same

Abstract: An integrated circuit having high performance CMOS devices with good short channel effects may be made by forming a gate structure over a substrate; forming pocket implant regions and source/drain extensions in the substrate; forming spacers along sides of the gate structure; and thermal annealing the substrate when forming the spacers, the thermal annealing performed at an ultra-low temperature. An integrated circuit having high performance CMOS devices with low parasitic junction capacitance may be made by forming a gate structure over a substrate; forming pocket implant regions and source/drain extensions in the substrate; forming spacers along sides of the gate structure; performing a low dosage source/drain implant; and performing a high dosage source/drain implant.

Ion-cut silicon-on-insulator fabrication with plasma immersion ion implantation

Abstract: We report the implementation of ion-cut silicon-on-insulator (SOI) wafer fabrication technique with plasma immersion ion implantation (PIII). The hydrogen implantation rate, which is independent of the wafer size, is considerably higher than that of conventional implantation. The simple PIII reactor setup and its compatibility with cluster-tools offer other ion-cut process optimization opportunities. The feasibility of the PIII ion-cut process is demonstrated by successful fabrication of SOI structures. The hydrogen plasma can be optimized so that only one ion species is dominant. The feasibility of performing ion-cut using helium PIII is also demonstrated.

Dual-metal gate technology for deep-submicron CMOS transistors

Abstract: Dual-metal gate CMOS devices with rapid-thermal chemical vapor deposited (RTCVD) Si/sub 3/N/sub 4/ gate dielectric were fabricated using a self-aligned process. The gate electrodes are Ti and Mo for the N- and P-MOSFET respectively. Carrier mobilities are comparable to that predicted by the universal mobility model for SiO/sub 2/. C-V characteristics show good agreement with a simulation that takes quantum-mechanical effects into account, and clearly display the advantage of metal over poly-Si gates.

Bsim4 and Mosfet Modeling for IC Simulation

Abstract: This book presents the art of advanced MOSFET modeling for integrated circuit simulation and design. It provides the essential mathematical and physical analyses of all the electrical, mechanical and thermal effects in MOS transistors relevant to the operation of integrated circuits. Particular emphasis is placed on how the BSIM model evolved into the first ever industry standard SPICE MOSFET model for circuit simulation and CMOS technology development. The discussion covers the theory and methodology of how a MOSFET model, or semiconductor device models in general, can be implemented to be robust and efficient, turning device physics theory into a production-worthy SPICE simulation model. Special attention is paid to MOSFET characterization and model parameter extraction methodologies, making the book particularly useful for those interested or already engaged in work in the areas of semiconductor devices, compact modeling for SPICE simulation, and integrated circuit design.

VIA-4 avalanche-induced breakdown mechanisms in short-channel MOSFETs

Abstract: The presence of oxide/semiconductor interface trapped charge (ITC) and its spatial nonuniformity can adversely affect the operation of MOSFETs. The advanced techniques which are used to fabricate circuits with devices of submicrometer geometries make use of radiation which can alter the number and charge state of these defects and modify the device operating characteristics. The traditional methods of measurement of ITC involve the use of large MOS capacitors to obtain accurate values for ITC. Since the processing history of these structures can differ substantially from the processing of typical MOSFETs, the values of ITC obtained from capacitors are often significantly different from the values measured on MOSFETs. Three direct methods for the measurement of ITC using short-channel MOSFETs have been evaluated: 1) the weak inversion method [l], 2) the use of the slope of the subthreshold current [21 and 3) the charge pump method Dl. The weak inversion method breaks down for short-channel transistors because the on-set of saturation in short-channel transistors is not clearly defined. The use of the slope of the subthreshold current is obscured ' by drain induced subthreshold current components. The charge pump method makes use of current produced by repetitively pulsing the channel of a MOSEET from accumulation to inversion and measuring the resulting current produced in an external circuit. When the pulse inverts the substrate, carriers from the source and drain form the substrate inversion layer. These carriers are trapped in the interface de e ts. During accumulation, it is assumed that all the excess mobile carriers in the inversion layer return to the source and drain and the charge pump current is due to the exchange of charge between the interface traps and the bulk silicon. In short-channel devices, this assumption is met. Only the channel width, length, and measurement frequency are required to calculate the ITC density from the charge pump current. Using detailed two-dimensional calculations of the channel inversion shape in short-channel transistors, we have shown that the channel length required for this measurement can be obtained, in a self aligned process, from the gate length. Using an automated parametric test system, the spatial variation of ITC across wafers was measured on pand nchannel MOSFETs fabricated using a self aligned CMOS bulk process. The mean value of ITC for the p-channel device (6.6 X 10" cmV2) was twice the mean for the n-channel device (3.3 X 10" cm-2). This suggest that boron contamination from the source/drain in the p-channel device may contribute to the difference in ITC.

I and i

Abstract: There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality. Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

疟原虫var基因转换速率变化导致抗原变异[英]／Paul H, Robert P, Christodoulou Z, et al//Proc Natl Acad Sci U S A

Abstract: 抗原变异可使得多种致病微生物易于逃避宿主免疫应答。表达在感染红细胞表面的恶性疟原虫红细胞表面蛋白1（PfPMP1）与感染红细胞、内皮细胞、树突状细胞以及胎盘的单个或多个受体作用，在黏附及免疫逃避中起关键的作用。每个单倍体基因组var基因家族编码约60种成员，通过启动转录不同的var基因变异体为抗原变异提供了分子基础。

High-κ gate dielectrics: Current status and materials properties considerations

Abstract: Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.1 μm complementary metal–oxide–semiconductor (CMOS) technology. A systematic consideration of the required properties of gate dielectrics indicates that the key guidelines for selecting an alternative gate dielectric are (a) permittivity, band gap, and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. A review of current work and literature in the area of alternate gate dielectrics is given. Based on reported results and fundamental considerations, the pseudobinary materials systems offer large flexibility and show the most promise toward success...

Design of Analog CMOS Integrated Circuits

Abstract: The CMOS technology area has quickly grown, calling for a new text--and here it is, covering the analysis and design of CMOS integrated circuits that practicing engineers need to master to succeed. Filled with many examples and chapter-ending problems, the book not only describes the thought process behind each circuit topology, but also considers the rationale behind each modification. The analysis and design techniques focus on CMOS circuits but also apply to other IC technologies. Table of contents 1 Introduction to Analog Design 2 Basic MOS Device Physics 3 Single-Stage Amplifiers 4 Differential Amplifiers 5 Passive and Active Current Mirrors 6 Frequency Response of Amplifiers 7 Noise 8 Feedback 9 Operational Amplifiers 10 Stability and Frequency Compensation 11 Bandgap References 12 Introduction to Switched-Capacitor Circuits 13 Nonlinearity and Mismatch 14 Oscillators 15 Phase-Locked Loops 16 Short-Channel Effects and Device Models 17 CMOS Processing Technology 18 Layout and Packaging

Prospects of Colloidal Nanocrystals for Electronic and Optoelectronic Applications

Abstract: Nanocrystals (NCs) discussed in this Review are tiny crystals of metals, semiconductors, and magnetic material consisting of hundreds to a few thousand atoms each. Their size ranges from 2-3 to about 20 nm. What is special about this size regime that placed NCs among the hottest research topics of the last decades? The quantum mechanical coupling * To whom correspondence should be addressed. E-mail: dvtalapin@uchicago.edu. † The University of Chicago. ‡ Argonne National Lab. Chem. Rev. 2010, 110, 389–458 389