Author
Chenming Hu
Other affiliations: Motorola, National Chiao Tung University, Semtech ...read more
Bio: Chenming Hu is an academic researcher from University of California, Berkeley. The author has contributed to research in topics: MOSFET & Gate oxide. The author has an hindex of 119, co-authored 1296 publications receiving 57264 citations. Previous affiliations of Chenming Hu include Motorola & National Chiao Tung University.
Topics: MOSFET, Gate oxide, CMOS, Gate dielectric, Transistor
Papers published on a yearly basis
Papers
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11 Apr 1994
TL;DR: In this paper, the physics of voltage and temperature accelerated breakdown testing of silicon dioxide within the framework of an anode hole injection model which can predict low voltage (3.3 V and below) breakdown lifetime.
Abstract: This paper investigates the physics of voltage and temperature accelerated breakdown testing of silicon dioxide within the framework of an anode hole injection model which can predict low voltage (3.3 V and below) breakdown lifetime. The field acceleration rate is shown to be independent of temperature, while the reduction of oxide breakdown lifetime at increased temperature is due to the oxide's enhanced susceptibility to damage caused by the holes' transport through the oxide. This paper also investigates defect related breakdown, showing that defects can be mathematically modeled as effective thinning even for aggressively scaled oxides. The effective thickness statistic derived from ramp breakdown or high-field lifetime or charge-to-breakdown tests enables determination of the oxide integrity of a specific oxide technology. For 3.3 Volt operation, an oxide technology must provide an effective thickness of 44 /spl Aring/; for 2.5 Volt operation, 34 /spl Aring/. >
43 citations
TL;DR: In this article, the authors measured the mean lifetime of a Cu/SiO2 interconnect with a test via and showed a significant increase in mean lifetime for structures in which the liner thickness at the base of the test via was less than approximately 6 nm, with a current density <5 mA/μm2 in the power line connected to the via.
Abstract: Electromigration lifetime was measured as a function of liner thickness for Cu/SiO2 interconnect structures. A significant increase in mean lifetime was observed for structures in which the liner thickness at the base of the test via was less than approximately 6 nm, with a current density <5 mA/μm2 in the power line connected to the test via. This is attributed to the continuous flow of Cu across the thin and possibly discontinuous liner at the base of the via. For extremely thin liner coverage, <1.4 nm at the base of the via and 2.5 at the bottom of the test line, the mean lifetime was observed to decrease as a rapid diffusion path was created which partially offset the beneficial effects of continuous flow. Failure distributions appeared to be trimodal and this was confirmed through failure analysis. In the case of thin liner coverage (<6 nm), early fails, which are typically characterized by slitlike voids at the via/line interface, were not observed.
42 citations
TL;DR: In this article, a thermal network extraction methodology to characterize self-heating effect using two-port RF measurements is presented, and the technique of determining isothermal condition using only the selfheating (thermal) dominated range of the spectrum.
Abstract: In this letter, we present a thermal network extraction methodology to characterize self-heating effect using two-port RF measurements. We show the technique of determining isothermal condition using only the self-heating (thermal) dominated range of the spectrum. We use a self-consistent self-heating extraction scheme using both the real and imaginary parts of drain port admittance parameters. Appropriate thermal network is investigated, and a large amount of temperature rise due to self-heating is confirmed for short channel silicon-on-insulator MOSFETs with ultrathin body and buried oxide.
42 citations
TL;DR: In this article, a metal-gate Si-QD nonvolatile memory (NVM) with program/erase speed of 1μs under low operating voltages of ± 7
Abstract: The ultrafast metal-gate silicon quantum-dot (Si-QD) nonvolatile memory (NVM) with program/erase speed of 1 μs under low operating voltages of ± 7 V is achieved by thin tunneling oxide, in situ Si-QD-embedded dielectrics, and metal gate. Selective source/drain activation by green nanosecond laser spike annealing, due to metal-gate as light-blocking layer, responds to low thermal damage on gate structures and, therefore, suppresses re-crystallization/deformation/diffusion of embedded Si-QDs. Accordingly, it greatly sustains efficient charge trapping/de-trapping in numerous deep charge-trapping sites in discrete Si-QDs. Such a gate nanostructure also ensures excellent endurance and retention in the microsecond-operation Si-QD NVM.
42 citations
11 Apr 1994
TL;DR: In this article, the ESD protection capability of SOI CMOS output buffers has been studied with human body model (HBM) stresses of both positive and negative polarity, and it has been shown that the discharge current is absorbed by the NMOSFET alone.
Abstract: ESD protection capability of SOI CMOS output buffers has been studied with human body model (HBM) stresses of both positive and negative polarity. Experimental results show that the ESD discharge current is absorbed by the NMOSFET alone. Unlike bulk technologies where the bi-directional ESD failure voltages are limited by positive polarity stresses, SOI circuits display a more serious reliability problem in handling negative ESD discharge current. Bulk NMOS output buffers fabricated on the substrate of the same SOI wafers, after etching away the buried oxide, have been used to compare the ESD protection capability between bulk and SOI technologies. The ESD voltage sustained by these "bulk" NMOS buffers is about twice the voltage sustained by conventional SOI NMOS buffers. This scheme is proposed as an alternative ESD protection for SOI circuits. The effectiveness of ESD resistant design strategies developed in bulk-substrate technologies when transferred to SOI circuits is also discussed in this paper. >
42 citations
Cited by
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[...]
TL;DR: There is, I think, something ethereal about i —the square root of minus one, which seems an odd beast at that time—an intruder hovering on the edge of reality.
Abstract: There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.
Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …
33,785 citations
28 Jul 2005
TL;DR: PfPMP1）与感染红细胞、树突状组胞以及胎盘的单个或多个受体作用，在黏附及免疫逃避中起关键的作�ly.
Abstract: 抗原变异可使得多种致病微生物易于逃避宿主免疫应答。表达在感染红细胞表面的恶性疟原虫红细胞表面蛋白1（PfPMP1）与感染红细胞、内皮细胞、树突状细胞以及胎盘的单个或多个受体作用，在黏附及免疫逃避中起关键的作用。每个单倍体基因组var基因家族编码约60种成员，通过启动转录不同的var基因变异体为抗原变异提供了分子基础。
18,940 citations
TL;DR: In this paper, a review of the literature in the area of alternate gate dielectrics is given, based on reported results and fundamental considerations, the pseudobinary materials systems offer large flexibility and show the most promise toward success.
Abstract: Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.1 μm complementary metal–oxide–semiconductor (CMOS) technology. A systematic consideration of the required properties of gate dielectrics indicates that the key guidelines for selecting an alternative gate dielectric are (a) permittivity, band gap, and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. A review of current work and literature in the area of alternate gate dielectrics is given. Based on reported results and fundamental considerations, the pseudobinary materials systems offer large flexibility and show the most promise toward success...
5,711 citations
Book•
01 Jan 1999
TL;DR: The analysis and design techniques of CMOS integrated circuits that practicing engineers need to master to succeed can be found in this article, where the authors describe the thought process behind each circuit topology, but also consider the rationale behind each modification.
Abstract: The CMOS technology area has quickly grown, calling for a new text--and here it is, covering the analysis and design of CMOS integrated circuits that practicing engineers need to master to succeed. Filled with many examples and chapter-ending problems, the book not only describes the thought process behind each circuit topology, but also considers the rationale behind each modification. The analysis and design techniques focus on CMOS circuits but also apply to other IC technologies.
Table of contents
1 Introduction to Analog Design
2 Basic MOS Device Physics
3 Single-Stage Amplifiers
4 Differential Amplifiers
5 Passive and Active Current Mirrors
6 Frequency Response of Amplifiers
7 Noise
8 Feedback
9 Operational Amplifiers
10 Stability and Frequency Compensation
11 Bandgap References
12 Introduction to Switched-Capacitor Circuits
13 Nonlinearity and Mismatch
14 Oscillators
15 Phase-Locked Loops
16 Short-Channel Effects and Device Models
17 CMOS Processing Technology
18 Layout and Packaging
4,826 citations
TL;DR: Nanocrystals (NCs) discussed in this Review are tiny crystals of metals, semiconductors, and magnetic material consisting of hundreds to a few thousand atoms each that are among the hottest research topics of the last decades.
Abstract: Nanocrystals (NCs) discussed in this Review are tiny crystals of metals, semiconductors, and magnetic material consisting of hundreds to a few thousand atoms each. Their size ranges from 2-3 to about 20 nm. What is special about this size regime that placed NCs among the hottest research topics of the last decades? The quantum mechanical coupling * To whom correspondence should be addressed. E-mail: dvtalapin@uchicago.edu. † The University of Chicago. ‡ Argonne National Lab. Chem. Rev. 2010, 110, 389–458 389
3,720 citations