Chenming Hu

Bio: Chenming Hu is an academic researcher from University of California, Berkeley. The author has contributed to research in topics: MOSFET & Gate oxide. The author has an hindex of 119, co-authored 1296 publications receiving 57264 citations. Previous affiliations of Chenming Hu include Motorola & National Chiao Tung University.

New thermooptical measurement method and a comparison with other methods

Abstract: A simple and sensitive method of measuring the thermally induced index changes arising from absorption of a laser beam in a low-loss material is described. The sample is placed outside the laser cavity, but at the position of minimum radius of curvature of the wavefront, which is a confocal distance behind the waist. It is estimated that the method is sensitive enough to measure absorption coefficients of the order of 5 x 10(_6) cm(_1) and it is shown experimentally to have good accuracy on low-loss materials. A detailed comparison of sensitivity and accuracy estimates is given for the various published thermal-lens methods for measuring low absorption coefficients.Although the method is illustrated for the thermal effect, it is applicable to other nonlinear index changes induced by laser beams.

Germanium-source tunnel field effect transistors with record high I ON /I OFF

Abstract: Tunnel field effect transistors (TFETs) with record high I ON /I OFF ratio (≫106) for low-voltage (0.5V) operation are achieved by using germanium in the source region to achieve a small tunnel bandgap. The measured data are well explained by the theoretical band-to-band tunneling current model. Using the calibrated analytical model, the energy-delay performance of TFET-based technology is compared against that of conventional CMOS technology, at the 65nm node. The TFET is projected to provide dramatic improvement in energy efficiency for performance in the range up to ∼0.5GHz.

A spacer patterning technology for nanoscale CMOS

Abstract: A spacer patterning technology using a sacrificial layer and a chemical vapor deposition (CVD) spacer layer has been developed, and is demonstrated to achieve sub-7 nm structures with conventional dry etching. The minimum-sized features are defined not by the photolithography but by the CVD film thickness. Therefore, this technology yields critical dimension (CD) variations of minimum-sized features much smaller than that achieved by optical or e-beam lithography. In addition, it also provides a doubling of device density for a given lithography pitch. This method is used to pattern silicon fins for double-gate metal-oxide semiconductor field effect transistors (MOSFETs) (FinFETs) and gate electrode structures for ultrathin body MOSFETs. Process details are presented.

Sub-60mV-swing negative-capacitance FinFET without hysteresis

Abstract: In this work, we report the first Negative-Capacitance FinFET. ALD Hf042Zr058O2 is added on top of the FinFET's gate stack. The test devices have a floating internal gate that can be electrically probed. Direct measurement found the small-signal voltage amplified by 1.6X maximum at the internal gate in agreement with the improvement of the subthreshold swing (from 87 to 55mV/decade). ION increased by >25% for the IOFF. For the first time, we demonstrate that raising HfZrO2 ferroelectricity, by annealing at higher temperature, reduces and eliminates IV hysteresis and increases the voltage gain. These discoveries will guide future theoretical and experimental work.

Nanoscale CMOS spacer FinFET for the terabit era

Abstract: A spacer lithography process technology, which uses a sacrificial layer and spacer layer formed by chemical vapor deposition (CVD), has been developed. It has been applied to make a sub-40-nm Si-fin structure for a double-gate FinFET with conventional dry etching for the first time. The minimum-sized features are defined not by the photolithography but by the CVD film thickness. Therefore, this spacer lithography technology yields better critical dimension uniformity than conventional optical or e-beam lithography and defines smaller features beyond the limit of current lithography technology. It also provides a doubling of feature density for a given lithography pitch, which increases current by a factor of two. To demonstrate this spacer lithography technology, Si-fin structures have been patterned for planar double-gate CMOS FinFET devices.

I and i

Abstract: There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality. Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

疟原虫var基因转换速率变化导致抗原变异[英]／Paul H, Robert P, Christodoulou Z, et al//Proc Natl Acad Sci U S A

Abstract: 抗原变异可使得多种致病微生物易于逃避宿主免疫应答。表达在感染红细胞表面的恶性疟原虫红细胞表面蛋白1（PfPMP1）与感染红细胞、内皮细胞、树突状细胞以及胎盘的单个或多个受体作用，在黏附及免疫逃避中起关键的作用。每个单倍体基因组var基因家族编码约60种成员，通过启动转录不同的var基因变异体为抗原变异提供了分子基础。

High-κ gate dielectrics: Current status and materials properties considerations

Abstract: Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.1 μm complementary metal–oxide–semiconductor (CMOS) technology. A systematic consideration of the required properties of gate dielectrics indicates that the key guidelines for selecting an alternative gate dielectric are (a) permittivity, band gap, and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. A review of current work and literature in the area of alternate gate dielectrics is given. Based on reported results and fundamental considerations, the pseudobinary materials systems offer large flexibility and show the most promise toward success...

Design of Analog CMOS Integrated Circuits

Abstract: The CMOS technology area has quickly grown, calling for a new text--and here it is, covering the analysis and design of CMOS integrated circuits that practicing engineers need to master to succeed. Filled with many examples and chapter-ending problems, the book not only describes the thought process behind each circuit topology, but also considers the rationale behind each modification. The analysis and design techniques focus on CMOS circuits but also apply to other IC technologies. Table of contents 1 Introduction to Analog Design 2 Basic MOS Device Physics 3 Single-Stage Amplifiers 4 Differential Amplifiers 5 Passive and Active Current Mirrors 6 Frequency Response of Amplifiers 7 Noise 8 Feedback 9 Operational Amplifiers 10 Stability and Frequency Compensation 11 Bandgap References 12 Introduction to Switched-Capacitor Circuits 13 Nonlinearity and Mismatch 14 Oscillators 15 Phase-Locked Loops 16 Short-Channel Effects and Device Models 17 CMOS Processing Technology 18 Layout and Packaging

Prospects of Colloidal Nanocrystals for Electronic and Optoelectronic Applications

Abstract: Nanocrystals (NCs) discussed in this Review are tiny crystals of metals, semiconductors, and magnetic material consisting of hundreds to a few thousand atoms each. Their size ranges from 2-3 to about 20 nm. What is special about this size regime that placed NCs among the hottest research topics of the last decades? The quantum mechanical coupling * To whom correspondence should be addressed. E-mail: dvtalapin@uchicago.edu. † The University of Chicago. ‡ Argonne National Lab. Chem. Rev. 2010, 110, 389–458 389