C
Chenming Hu
Researcher at University of California, Berkeley
Publications - 1300
Citations - 60963
Chenming Hu is an academic researcher from University of California, Berkeley. The author has contributed to research in topics: MOSFET & Gate oxide. The author has an hindex of 119, co-authored 1296 publications receiving 57264 citations. Previous affiliations of Chenming Hu include Motorola & National Chiao Tung University.
Papers
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Proceedings ArticleDOI
Comparison of ESD protection capability of SOI and bulk CMOS output buffers
TL;DR: In this article, the ESD protection capability of SOI CMOS output buffers has been studied with human body model (HBM) stresses of both positive and negative polarity, and it has been shown that the discharge current is absorbed by the NMOSFET alone.
Journal ArticleDOI
Accurate determination of ultrathin gate oxide thickness and effective polysilicon doping of CMOS devices
TL;DR: In this paper, the authors used Fowler-Nordheim (F-N) tunneling current across the gate oxide with correction in gate voltage to account for the polysilicon-gate depletion.
Patent
Bonded soi wafer with device layer and substrate for performance improvement
TL;DR: In this paper, a new silicon structure is provided, where a first silicon substrate having a crystallographic orientation is bonded to the surface of a second silicon substrate with a different orientation, and the wafer alignment notch of the first and the second silicon substrates are aligned with each other.
Journal ArticleDOI
Electromigration in two-level interconnect structures with Al alloy lines and W studs
TL;DR: In this article, it was shown that the mass depletion of Al has a strong effect on the resistance change and electromigration failure in line/stud chains, leading to a slower motion and the production of extrusions.
Proceedings ArticleDOI
MOS memory using germanium nanocrystals formed by thermal oxidation of Si/sub 1-x/Ge/sub x/
TL;DR: In this article, a novel technique of fabricating germanium nanocrystal quasi-nonvolatile memory devices was proposed, which consists of a MOSFET with Ge charge-traps embedded within the gate dielectric.