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Author

Chenming Hu

Other affiliations: Motorola, National Chiao Tung University, Semtech  ...read more
Bio: Chenming Hu is an academic researcher from University of California, Berkeley. The author has contributed to research in topics: MOSFET & Gate oxide. The author has an hindex of 119, co-authored 1296 publications receiving 57264 citations. Previous affiliations of Chenming Hu include Motorola & National Chiao Tung University.
Topics: MOSFET, Gate oxide, CMOS, Gate dielectric, Transistor


Papers
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Journal ArticleDOI
01 Nov 2003
TL;DR: Key elements of silicon-based CMOS technologies are described, including sublithographic patterning, the effects of crystal orientation and roughness on carrier mobility, gate work function engineering, circuit performance, and sensitivity to process-induced variations.
Abstract: Silicon-based CMOS technology can be scaled well into the nanometer regime. High-performance, planar, ultrathin-body devices fabricated on silicon-on-insulator substrates have been demonstrated down to 15-nm gate lengths. We have also introduced the FinFET, a double-gate device structure that is relatively simple to fabricate and can be scaled to gate lengths below 10 nm. In this paper, some of the key elements of these technologies are described, including sublithographic patterning, the effects of crystal orientation and roughness on carrier mobility, gate work function engineering, circuit performance, and sensitivity to process-induced variations.

264 citations

Journal ArticleDOI
TL;DR: In this article, the authors demonstrate 2D-2D tunneling in a WSe2/SnSe2 van der Waals vertical heterojunction device, where WSe 2 is used as the gate controlled p-layer and SnSe2 is the degenerately n-type layer.
Abstract: Two-dimensional materials present a versatile platform for developing steep transistors due to their uniform thickness and sharp band edges. We demonstrate 2D-2D tunneling in a WSe2/SnSe2 van der Waals vertical heterojunction device, where WSe2 is used as the gate controlled p-layer and SnSe2 is the degenerately n-type layer. The van der Waals gap facilitates the regulation of band alignment at the heterojunction, without the necessity of a tunneling barrier. ZrO2 is used as the gate dielectric, allowing the scaling of gate oxide to improve device subthreshold swing. Efficient gate control and clean interfaces yield a subthreshold swing of ∼100 mV/dec for >2 decades of drain current at room temperature, hitherto unobserved in 2D-2D tunneling devices. The subthreshold swing is independent of temperature, which is a clear signature of band-to-band tunneling at the heterojunction. A maximum switching ratio ION/IOFF of 107 is obtained. Negative differential resistance in the forward bias characteristics is observed at 77 K. This work bodes well for the possibilities of two-dimensional materials for the realization of energy-efficient future-generation electronics.

252 citations

Journal ArticleDOI
24 Jan 2019-Nature
TL;DR: A direct measurement of steady-state negative capacitance in a ferroelectric–dielectric heterostructure is demonstrated using electron microscopy complemented by phase-field and first-principles-based (second- Principles) simulations in SrTiO3/PbTiO2 superlattices with atomic resolution.
Abstract: Negative capacitance is a newly discovered state of ferroelectric materials that holds promise for electronics applications by exploiting a region of thermodynamic space that is normally not accessible1–14. Although existing reports of negative capacitance substantiate the importance of this phenomenon, they have focused on its macroscale manifestation. These manifestations demonstrate possible uses of steady-state negative capacitance—for example, enhancing the capacitance of a ferroelectric–dielectric heterostructure4,7,14 or improving the subthreshold swing of a transistor8–12. Yet they constitute only indirect measurements of the local state of negative capacitance in which the ferroelectric resides. Spatial mapping of this phenomenon would help its understanding at a microscopic scale and also help to achieve optimal design of devices with potential technological applications. Here we demonstrate a direct measurement of steady-state negative capacitance in a ferroelectric–dielectric heterostructure. We use electron microscopy complemented by phase-field and first-principles-based (second-principles) simulations in SrTiO3/PbTiO3 superlattices to directly determine, with atomic resolution, the local regions in the ferroelectric material where a state of negative capacitance is stabilized. Simultaneous vector mapping of atomic displacements (related to a complex pattern in the polarization field), in conjunction with reconstruction of the local electric field, identify the negative capacitance regions as those with higher energy density and larger polarizability: the domain walls where the polarization is suppressed. Imaging steady-state negative capacitance in SrTiO3/PbTiO3 superlattices with atomic resolution provides solid microscale support for this phenomenon.

247 citations

Patent
Yee-Chia Yeo1, Chen How-Yu Hu1, Chien-Chao Huang1, Wen-Chin Lee1, Fu-Liang Yang1, Chenming Hu1 
30 Apr 2003
TL;DR: In this article, a planar SOI MOSFET including a strained channel region is formed on a first portion of the silicon layer, followed by a partially-depleted SOI (PD-SOI) layer.
Abstract: In accordance with a preferred embodiment of the present invention, a silicon-on-insulator (SOI) chip includes a silicon layer of a predetermined thickness overlying an insulator layer. A multiple-gate fully-depleted SOI MOSFET including a strained channel region is formed on a first portion of the silicon layer. A planar SOI MOSFET including a strained channel region formed on another portion of the silicon layer. For example, the planar SOI MOSFET can be a planar fully-depleted SOI (FD-SOI) MOSFET or the planar SOI MOSFET can be a planar partially-depleted SOI (PD-SOI) MOSFET.

246 citations

Proceedings ArticleDOI
01 Dec 2000
TL;DR: In this article, thin-body transistors with silicide source/drains were fabricated with gate-lengths down to 15 nm and complementary low-barrier silicides were used to reduce contact and series resistance.
Abstract: Thin-body transistors with silicide source/drains were fabricated with gate-lengths down to 15 nm. Complementary low-barrier silicides were used to reduce contact and series resistance. Minimum gate-length transistors with T/sub ox/=40 /spl Aring/ show PMOS |I/sub dsat/|=270 /spl mu/A//spl mu/m and NMOS |I/sub dsat/|=190 /spl mu/A//spl mu/m with V/sub ds/=1.5 V, |V/sub g/-V/sub t/|=1.2 V and, I/sub on//I/sub off/>10/sup 4/. A simple transmission model, fitted to experimental data, is used to investigate effects of oxide scaling and extension doping.

246 citations


Cited by
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Journal ArticleDOI

[...]

08 Dec 2001-BMJ
TL;DR: There is, I think, something ethereal about i —the square root of minus one, which seems an odd beast at that time—an intruder hovering on the edge of reality.
Abstract: There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality. Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

33,785 citations

28 Jul 2005
TL;DR: PfPMP1)与感染红细胞、树突状组胞以及胎盘的单个或多个受体作用,在黏附及免疫逃避中起关键的作�ly.
Abstract: 抗原变异可使得多种致病微生物易于逃避宿主免疫应答。表达在感染红细胞表面的恶性疟原虫红细胞表面蛋白1(PfPMP1)与感染红细胞、内皮细胞、树突状细胞以及胎盘的单个或多个受体作用,在黏附及免疫逃避中起关键的作用。每个单倍体基因组var基因家族编码约60种成员,通过启动转录不同的var基因变异体为抗原变异提供了分子基础。

18,940 citations

Journal ArticleDOI
TL;DR: In this paper, a review of the literature in the area of alternate gate dielectrics is given, based on reported results and fundamental considerations, the pseudobinary materials systems offer large flexibility and show the most promise toward success.
Abstract: Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.1 μm complementary metal–oxide–semiconductor (CMOS) technology. A systematic consideration of the required properties of gate dielectrics indicates that the key guidelines for selecting an alternative gate dielectric are (a) permittivity, band gap, and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. A review of current work and literature in the area of alternate gate dielectrics is given. Based on reported results and fundamental considerations, the pseudobinary materials systems offer large flexibility and show the most promise toward success...

5,711 citations

Book
01 Jan 1999
TL;DR: The analysis and design techniques of CMOS integrated circuits that practicing engineers need to master to succeed can be found in this article, where the authors describe the thought process behind each circuit topology, but also consider the rationale behind each modification.
Abstract: The CMOS technology area has quickly grown, calling for a new text--and here it is, covering the analysis and design of CMOS integrated circuits that practicing engineers need to master to succeed. Filled with many examples and chapter-ending problems, the book not only describes the thought process behind each circuit topology, but also considers the rationale behind each modification. The analysis and design techniques focus on CMOS circuits but also apply to other IC technologies. Table of contents 1 Introduction to Analog Design 2 Basic MOS Device Physics 3 Single-Stage Amplifiers 4 Differential Amplifiers 5 Passive and Active Current Mirrors 6 Frequency Response of Amplifiers 7 Noise 8 Feedback 9 Operational Amplifiers 10 Stability and Frequency Compensation 11 Bandgap References 12 Introduction to Switched-Capacitor Circuits 13 Nonlinearity and Mismatch 14 Oscillators 15 Phase-Locked Loops 16 Short-Channel Effects and Device Models 17 CMOS Processing Technology 18 Layout and Packaging

4,826 citations

Journal ArticleDOI
TL;DR: Nanocrystals (NCs) discussed in this Review are tiny crystals of metals, semiconductors, and magnetic material consisting of hundreds to a few thousand atoms each that are among the hottest research topics of the last decades.
Abstract: Nanocrystals (NCs) discussed in this Review are tiny crystals of metals, semiconductors, and magnetic material consisting of hundreds to a few thousand atoms each. Their size ranges from 2-3 to about 20 nm. What is special about this size regime that placed NCs among the hottest research topics of the last decades? The quantum mechanical coupling * To whom correspondence should be addressed. E-mail: dvtalapin@uchicago.edu. † The University of Chicago. ‡ Argonne National Lab. Chem. Rev. 2010, 110, 389–458 389

3,720 citations