There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

抗原变异可使得多种致病微生物易于逃避宿主免疫应答。表达在感染红细胞表面的恶性疟原虫红细胞表面蛋白1（PfPMP1）与感染红细胞、内皮细胞、树突状细胞以及胎盘的单个或多个受体作用，在黏附及免疫逃避中起关键的作用。每个单倍体基因组var基因家族编码约60种成员，通过启动转录不同的var基因变异体为抗原变异提供了分子基础。

疟原虫var基因转换速率变化导致抗原变异[英]／Paul H, Robert P, Christodoulou Z, et al//Proc Natl Acad Sci U S A

Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.1 μm complementary metal–oxide–semiconductor (CMOS) technology. A systematic consideration of the required properties of gate dielectrics indicates that the key guidelines for selecting an alternative gate dielectric are (a) permittivity, band gap, and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. A review of current work and literature in the area of alternate gate dielectrics is given. Based on reported results and fundamental considerations, the pseudobinary materials systems offer large flexibility and show the most promise toward success...

/pdf/high-k-gate-dielectrics-current-status-and-materials-zjvba0c4u8.pdf

High-κ gate dielectrics: Current status and materials properties considerations

The CMOS technology area has quickly grown, calling for a new text--and here it is, covering the analysis and design of CMOS integrated circuits that practicing engineers need to master to succeed. Filled with many examples and chapter-ending problems, the book not only describes the thought process behind each circuit topology, but also considers the rationale behind each modification. The analysis and design techniques focus on CMOS circuits but also apply to other IC technologies.
Table of contents

1 Introduction to Analog Design
2 Basic MOS Device Physics
3 Single-Stage Amplifiers
4 Differential Amplifiers
5 Passive and Active Current Mirrors
6 Frequency Response of Amplifiers
7 Noise
8 Feedback
9 Operational Amplifiers
10 Stability and Frequency Compensation
11 Bandgap References
12 Introduction to Switched-Capacitor Circuits
13 Nonlinearity and Mismatch
14 Oscillators
15 Phase-Locked Loops
16 Short-Channel Effects and Device Models
17 CMOS Processing Technology
18 Layout and Packaging

/pdf/design-of-analog-cmos-integrated-circuits-35wxhwa3a6.pdf

Design of Analog CMOS Integrated Circuits

Nanocrystals (NCs) discussed in this Review are tiny crystals of metals, semiconductors, and magnetic material consisting of hundreds to a few thousand atoms each. Their size ranges from 2-3 to about 20 nm. What is special about this size regime that placed NCs among the hottest research topics of the last decades? The quantum mechanical coupling * To whom correspondence should be addressed. E-mail: dvtalapin@uchicago.edu. † The University of Chicago. ‡ Argonne National Lab. Chem. Rev. 2010, 110, 389–458 389

/pdf/prospects-of-colloidal-nanocrystals-for-electronic-and-3dxpyhl3r7.pdf

Prospects of Colloidal Nanocrystals for Electronic and Optoelectronic Applications

In this paper a computationally efficient surface-potential-based compact model for fully-depleted SOI MOSFETs with independently-controlled front- and back-gates is presented. A fully-depleted SOI MOSFET with a back-gate is essentially an independent double-gate device. To the best of our knowledge, existing surface-potential-based models for independent double-gate devices require numerical iteration to compute the surface potentials. This increases the model computational time and may cause convergence difficulties. In this work, a new approximation scheme is developed to compute the surface potentials and charge densities using explicit analytical equations. The approximation is shown to be computationally efficient and preserves important properties of fully-depleted SOI MOSFETs such as volume inversion. Drain current and charge expressions are derived without using the charge sheet approximation and agree well with TCAD simulations. Non-ideal effects are added to describe the I–V and C–V of a real device. Source-drain symmetry is preserved for both the current and the charge models. The full model is implemented in Verilog-A and its convergence is demonstrated through transient simulation of a coupled ring oscillator circuit with 2020 transistors.

A computationally efficient compact model for fully-depleted SOI MOSFETs with independently-controlled front- and back-gates

BSIM-CMG 108.0.0: Multi-gate MOSFET compact model: technical manual

The authors present simulation results, an experimental technique, and a model for estimating the temperature rise and time-to-failure (TTF) of interconnect They introduce the concept of derating factor for electromigration TTF due to self-heating The derating factor is the factor by which the lifetime is reduced by temperature rise in the interconnect It is shown that in the limit of high frequencies, the temperature rise can be estimated in a straightforward manner using the root-mean-square current density after the thermal resistance of the structure has been determined from DC measurements The implication of the temperature dependence on J/sub rms/ for the usually quoted J/sub ave/ design rule was examined It was determined that self-heating is probably not significant for the usual design rule average current density of 1*10/sup 5/ A/cm/sup 2/ for operation at frequencies >10 MHz and duty factors >01% However, if the design rule is increased to 1*10/sup 6/ A/cm/sup 2/, self-heating might become significant >

Effects of self-heating on integrated circuit metallization lifetimes

On-chip global interconnect exhibits clear frequency dependence in both resistance (R) and inductance ( L). In this paper, its impact on modern digital and radio frequency (RF) circuit design is examined. First, a physical and compact ladder circuit model is developed to capture this behavior, which only employs frequency independent R and L elements, and thus, supports transient analysis. Using this new model we demonstrate that the use of dc values for R and L is sufficient for timing analysis (i.e., 50% delay and slew rate) in digital designs. However, RL frequency dependence is critical for the analysis of signal integrity, shield line insertion, power supply stability, and RF inductor performance.

Impact of on-chip interconnect frequency-dependent R(f)L(f) on digital and RF design

We have successfully developed a new quantitative ITAT (inelastic trap-assisted tunneling) based SILC (stress induced leakage current) model by introducing traps with a deep energy level of around 4.0 eV which can explain two field dependencies, i.e. Fowler-Nordheim (FN) field and the direct tunneling (DT) field dependence. For simple analytical models, we introduce the most favorable trap position, which gives the largest contribution to the leakage current. A-mode and B-mode SILC are the leakage currents in the nominal oxide region and at the weak oxide spots, respectively, which can be deduced by the large difference in the area density between the single trap area (/spl sim/1/spl times/10/sup 11/ cm/sup -2/) and the multi-trap path (/spl sim/1/spl times/10/sup 2/ cm/sup -2/). Our model suggests that for flash EPROM, a 13 nm-oxide thickness is required for 1.0 fC on the floating gate to last 100 years.

Chenming Hu

Papers

A computationally efficient compact model for fully-depleted SOI MOSFETs with independently-controlled front- and back-gates

BSIM-CMG 108.0.0: Multi-gate MOSFET compact model: technical manual

Effects of self-heating on integrated circuit metallization lifetimes

Impact of on-chip interconnect frequency-dependent R(f)L(f) on digital and RF design

Deep-trap SILC (stress induced leakage current) model for nominal and weak oxides