Chetan Kumar Dabhi

Bio: Chetan Kumar Dabhi is an academic researcher from Indian Institute of Technology Kanpur. The author has contributed to research in topics: Transistor & MOSFET. The author has an hindex of 5, co-authored 17 publications receiving 95 citations. Previous affiliations of Chetan Kumar Dabhi include Indian Institutes of Technology & Sardar Vallabhbhai National Institute of Technology, Surat.

Impact of Variability on Processor Performance in Negative Capacitance FinFET Technology

Abstract: In this work, we investigate for the first time the impact of Negative Capacitance FinFET (NC-FinFET) technology on the performance of processors under the effects of process variations for various operating voltages. The industry compact model of FinFETs (BSIM-CMG) is fully calibrated to reproduce Intel 14nm FinFET data of high volume manufacturing process. A physics-based negative capacitance (NC) model is integrated and solved self-consistently within the BSIM-CMG model. This allows the creation of NC-FinFET standard cell libraries, while considering the effects of various variability sources both in the ferroelectric layer as well as in the underlying constituent FinFET device. The variability-aware NC-FinFET libraries, fully compatible with the existing standard design flow of circuits, are then employed to perform simulations using commercial statistical timing analysis tools in order to study the performance of a 14nm processor. For comprehensive analysis and comparisons, our implementation is done for both NC-FinFET and conventional (baseline) FinFET for a wide range of voltages. Our results demonstrate that process variations have a larger impact on the processor’s performance in NC-FinFET – when it operates at a lower voltage compared to the baseline FinFET that still operates at the nominal high voltage – due to the additional ferroelectric-induced variability. Results also reveal that neglecting process variations leads to overestimating the benefit that NC brings to the processor’s frequency improvement because of the larger timing guardband that is needed to overcome variability in NC-FinFET.

A Simulation Study of NBTI Impact on 14-nm Node FinFET Technology for Logic Applications: Device Degradation to Circuit-Level Interaction

Abstract: A comprehensive simulation flow is demonstrated to assess the negative-bias temperature instability (NBTI) impact on the performance and power of digital logic circuits based on the 14-nm node FinFET technology. Fully calibrated technology computer-aided design simulations are used to determine the preaged and postaged device characteristics; the results are used for calibrating the BSIM-CMG compact model. Standard cell libraries are characterized next, by only threshold voltage shift ( $\Delta {V}_{\text {T}}$ ) and by both $\Delta {V}_{\text {T}}$ and subthreshold slope shift ( $\Delta $ SS). Various benchmark circuits are synthesized and analyzed, and their timing degradation is compared to ring oscillator results. The consequence of ignoring $\Delta $ SS on OFF current and static power ( ${P}_{\text {static}}$ ) is estimated.

Device to Circuit Framework for Activity-Dependent NBTI Aging in Digital Circuits

Abstract: A framework is proposed for activity-dependent timing degradation due to p-FET negative bias temperature instability (NBTI) in digital circuits. A fixed-time compact model is proposed for NBTI and validated with physical model predictions for various digital circuits under different input signal slew and fan-out load conditions. The model is used to predict the timing degradation in digital circuits under arbitrary input activities. An equivalent degradation level is found that can be applied to all p-FETs in the circuit and can serve as an upper bound of degradation due to arbitrary input activity and avoid the conservative worst case dc analysis. The activity dependence is studied in microprocessors as well as arithmetic circuits under different actual workloads.

Compact Modeling of Negative-Capacitance FDSOI FETs for Circuit Simulations

Abstract: The compact model for negative capacitance FDSOI (NC-FDSOI) FET with metal–ferroelectric–insulator–semiconductor (MFIS) gate-stack is presented, for the first time, in this article. The model is developed based on the framework of BSIM-IMG, an industry-standard model (i.e., for zero thickness of a ferroelectric layer, the model mimics the behavior of BSIM-IMG). The developed NC-FDSOI model is computationally efficient and captures drain current and its derivatives accurately. The model shows an excellent agreement with numerical simulation and the measured data of NC-FDSOI FET. The proposed compact model is implemented in Verilog-A and tested for circuit simulations using commercial circuit simulators.

Subthermionic negative capacitance ion sensitive field-effect transistor

Abstract: One of the main advantages of Ion-Sensitive Field-Effect Transistor (ISFET) technology is the capability to exploit technological advancements initially developed for conventional FETs for logic applications, such as the employ of high-k dielectrics for the gate and the definition of fully depleted and gate all around structures. Negative Capacitance (NC) is an emerging concept exploiting ferroelectric materials integrated in field effect transistor gate stacks in order to decrease their subthreshold swing and improve the drain current (ID) overdrive in order to reach more energy efficient devices, operated at lower voltage. In this work, we investigate and experimentally demonstrate the application of this concept to enable subthermionic ISFETs with enhanced current sensitivity and low power operation. A physical model for the introduced NC ISFET is presented and optimized by fitting of the experimental results, providing further insights into the sensor parameters and a predictive tool for the design of future NC-based sensors.

Compact modeling of high-voltage LDMOS devices including quasi-saturation

Abstract: The surface-potential-based compact transistor model, MOS Model 20 (MM20), has been extended with a quasi-saturation, an effect that is typical for LDMOS devices with a long drift region As a result, MM20 extends its application range from low-voltage LDMOS devices up to high-voltage LDMOS devices of about 100V In this paper, the new dc model of MM20, including quasi-saturation, is presented The addition of velocity saturation in the drift region ensures the current to be controlled by either the channel region or the drift region A comparison with dc measurements on a 60-V LDMOS device shows that the new model provides an accurate description in all regimes of operation, ranging from subthreshold to superthreshold, in both the linear and saturation regime Thus, owing to the inclusion of quasi-saturation also the regime of high-gate and high-drain bias conditions for high-voltage LDMOS devices is accurately described

Impact of Variability on Processor Performance in Negative Capacitance FinFET Technology

Abstract: In this work, we investigate for the first time the impact of Negative Capacitance FinFET (NC-FinFET) technology on the performance of processors under the effects of process variations for various operating voltages. The industry compact model of FinFETs (BSIM-CMG) is fully calibrated to reproduce Intel 14nm FinFET data of high volume manufacturing process. A physics-based negative capacitance (NC) model is integrated and solved self-consistently within the BSIM-CMG model. This allows the creation of NC-FinFET standard cell libraries, while considering the effects of various variability sources both in the ferroelectric layer as well as in the underlying constituent FinFET device. The variability-aware NC-FinFET libraries, fully compatible with the existing standard design flow of circuits, are then employed to perform simulations using commercial statistical timing analysis tools in order to study the performance of a 14nm processor. For comprehensive analysis and comparisons, our implementation is done for both NC-FinFET and conventional (baseline) FinFET for a wide range of voltages. Our results demonstrate that process variations have a larger impact on the processor’s performance in NC-FinFET – when it operates at a lower voltage compared to the baseline FinFET that still operates at the nominal high voltage – due to the additional ferroelectric-induced variability. Results also reveal that neglecting process variations leads to overestimating the benefit that NC brings to the processor’s frequency improvement because of the larger timing guardband that is needed to overcome variability in NC-FinFET.

Impact of Extrinsic Variation Sources on the Device-to-Device Variation in Ferroelectric FET

Abstract: Variation due to the intrinsic ferroelectric switching process has been known to cause serious challenges for the FeFET variation control This work complements that understanding by investigating, for the first time, the impact of extrinsic variation sources on the variation of FeFETs We show that: 1) poorer electrostatics in a FeFET due to a thicker oxide does not degrade the overall variation when comparing to a baseline FinFET with an equal oxide thickness as the FeFET and a thin oxide reference transistor; 2) variation sources from the ferroelectric parameters constitute a significant portion in the overall FeFET variation, whereas the underlying transistor variation is marginal These results highlight that besides the intrinsic ferroelectric switching control, ferroelectric parameters uniformity should also be one of the primary optimization targets towards building reliable FeFET-based non-volatile memory

NPU Thermal Management

Abstract: Neural processing units (NPUs) are becoming an integral part in all modern computing systems due to their substantial role in accelerating neural networks (NNs). The significant improvements in cost-energy-performance stem from the massive array of multiply accumulate (MAC) units that remarkably boosts the throughput of NN inference. In this work, we are the first to investigate the thermal challenges that NPUs bring, revealing how MAC arrays, which form the heart of any NPU, impose serious thermal bottlenecks to on-chip systems due to their excessive power densities. For the first time, we explore: 1) the effectiveness of precision scaling and frequency scaling (FS) in temperature reductions and 2) how advanced on-chip cooling using superlattice thin-film thermoelectric (TE) open doors for new tradeoffs between temperature, throughput, cooling cost, and inference accuracy in NPU chips. Our work unveils that hybrid thermal management , which composes different means to reduce the NPU temperature, is a key. To achieve that, we propose and implement PFS-TE technique that couples precision and FS together with superlattice TE cooling for effective NPU thermal management. Using commercial signoff tools, we obtain accurate power and timing analysis of MAC arrays after a full-chip design is performed based on 14-nm Intel FinFET technology. Then, multiphysics simulations using finite-element methods are carried out for accurate heat simulations in the presence and absence of on-chip cooling. Afterward, comprehensive design-space exploration is presented to demonstrate the Pareto frontier and the existing tradeoffs between temperature reductions, power overheads due to cooling, throughput, and inference accuracy. Using a wide range of NNs trained for image classification, experimental results demonstrate that our novel NPU thermal management increases the inference efficiency (TOPS/Joule) by $1.33\times $ , $1.87\times $ , and $2\times $ under different temperature constraints; 105 °C, 85 °C, and 70 °C, respectively, while the average accuracy drops merely from 89.0% to 85.5%.

Modeling of Semiconductor Electrostatic Qubits Realized Through Coupled Quantum Dots

Abstract: Considering the enormous advances in nanometer-scale CMOS technology that now allows one to reliably fabricate billions of switching devices on a single silicon die, electrostatically controlled quantum dots (implemented as quantum wells) appear to be promising candidates for a massive implementation of quantum bits (qubits) and quantum logic circuits in order to facilitate high-volume production of quantum computers. In this paper, the case of finite two-well and multiple-well potentials arising from semiconductor charged-coupled structures are treated in a rigorous way by Schrodinger formalism. The modeling methodologies presented to allow one to describe the dynamics of quantum states in non-ideal geometries, account for some mechanisms of qubit decoherence and model electrostatic interaction between electrons that lead to entanglement. The presented methodology can be scaled up to circuits of greater complexity.