Chetan Prasad

Bio: Chetan Prasad is an academic researcher from Intel. The author has contributed to research in topics: Quantum dot & PMOS logic. The author has an hindex of 16, co-authored 58 publications receiving 1951 citations. Previous affiliations of Chetan Prasad include Arizona State University.

A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging

Abstract: A 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process. The transistors feature 1.0 nm EOT high-k gate dielectric, dual band edge workfunction metal gates and third generation strained silicon, resulting in the highest drive currents yet reported for NMOS and PMOS. The technology also features trench contact based local routing, 9 layers of copper interconnect with low-k ILD, low cost 193 nm dry patterning, and 100% Pb-free packaging. Process yield, performance and reliability are demonstrated on 153 Mb SRAM arrays with SRAM cell size of 0.346 mum2, and on multiple microprocessors.

BTI reliability of 45 nm high-K + metal-gate process technology

Abstract: In this paper, bias-temperature instability (BTI) characterization on 45nm high-K + metal-gate (HK+MG) transistors is presented and degradation mechanism is discussed. Transistors with an unoptimized HK film stack in the early development phase exhibited pre-existing traps and large amount of hysteresis that was consistent with literature. The optimized and final HK process demonstrated NMOS and PMOS BTI on HK+MG transistors that are better than that of SiON at matched E-fields and comparable at targeted 30% higher use fields. The final process also showed no hysteresis due to fast traps thereby allowing us to characterize its intrinsic degradation mechanism. On the optimized process, NMOS BTI is attributed primarily to electron trapping in the HK bulk and HK/SiON interfacial layer (IL) regions. PMOS BTI degradation, on the other hand, is mainly interface driven and is found to be very similar to that observed on conventional SiON transistors.

Self-heat reliability considerations on Intel's 22nm Tri-Gate technology

Abstract: This paper describes various measurements on self-heat performed on Intel's 22nm process technology, and outlines its reliability implications. Comparisons to thermal modeling results and analytical data show excellent matching.

Effect of BTI Degradation on Transistor Variability in Advanced Semiconductor Technologies

Abstract: The effect of PMOS transistor negative bias temperature instability (NBTI) on product performance is a key reliability concern. As technology scales and device dimensions shrink, the trend in the V T variability at both time zero and after NBTI aging increases. The time0 V T variability can be explained by the random nature of dopants, whereas the randomly generated defects in the gate oxide can account for the aging-induced device DeltaV T variability. This paper focuses on the bias temperature instability stress-induced device DeltaV T variability and the trend across several technology generations. The remarkable correlation of aging-induced DeltaV T variability to the gate oxide area suggests that the continued device geometry scaling will increase the aging-induced variability. For the first time, aging-induced DeltaV T variability was characterized on transistors fabricated with high-kappa gate dielectric that also showed similar dependence to the gate oxide area.

A 14 nm SoC platform technology featuring 2 nd generation Tri-Gate transistors, 70 nm gate pitch, 52 nm metal pitch, and 0.0499 um 2 SRAM cells, optimized for low power, high performance and high density SoC products

Abstract: A leading edge 14 nm SoC platform technology based upon the 2nd generation Tri-Gate transistor technology [5] has been optimized for density, low power and wide dynamic range. 70 nm gate pitch, 52 nm metal pitch and 0.0499 um2 HDC SRAM cells are the most aggressive design rules reported for 14/16 nm node SoC process to achieve Moore's Law 2x density scaling over 22 nm node. High performance NMOS/PMOS drive currents of 1.3/1.2 mA/um, respectively, have been achieved at 0.7 V and 100 nA/um off-state leakage, 37%/50% improvement over 22 nm node. Ultra-low power NMOS/PMOS drives are 0.50/0.32 mA/um at 0.7 V and 15pA/um Ioff. This technology also deploys high voltage I/O transistors to support up to 3.3 V I/O. A full suite of analog, mixed-signal and RF features are also supported.

Single-layer MoS2 transistors

Abstract: Two-dimensional materials are attractive for use in next-generation nanoelectronic devices because, compared to one-dimensional materials, it is relatively easy to fabricate complex structures from them. The most widely studied two-dimensional material is graphene, both because of its rich physics and its high mobility. However, pristine graphene does not have a bandgap, a property that is essential for many applications, including transistors. Engineering a graphene bandgap increases fabrication complexity and either reduces mobilities to the level of strained silicon films or requires high voltages. Although single layers of MoS(2) have a large intrinsic bandgap of 1.8 eV (ref. 16), previously reported mobilities in the 0.5-3 cm(2) V(-1) s(-1) range are too low for practical devices. Here, we use a halfnium oxide gate dielectric to demonstrate a room-temperature single-layer MoS(2) mobility of at least 200 cm(2) V(-1) s(-1), similar to that of graphene nanoribbons, and demonstrate transistors with room-temperature current on/off ratios of 1 × 10(8) and ultralow standby power dissipation. Because monolayer MoS(2) has a direct bandgap, it can be used to construct interband tunnel FETs, which offer lower power consumption than classical transistors. Monolayer MoS(2) could also complement graphene in applications that require thin transparent semiconductors, such as optoelectronics and energy harvesting.

Electronics based on two-dimensional materials

Abstract: The compelling demand for higher performance and lower power consumption in electronic systems is the main driving force of the electronics industry's quest for devices and/or architectures based on new materials. Here, we provide a review of electronic devices based on two-dimensional materials, outlining their potential as a technological option beyond scaled complementary metal-oxide-semiconductor switches. We focus on the performance limits and advantages of these materials and associated technologies, when exploited for both digital and analog applications, focusing on the main figures of merit needed to meet industry requirements. We also discuss the use of two-dimensional materials as an enabling factor for flexible electronics and provide our perspectives on future developments.

Use of Negative Capacitance to Provide Voltage Amplification for Low Power Nanoscale Devices

Abstract: It is well-known that conventional field effect transistors (FETs) require a change in the channel potential of at least 60 mV at 300 K to effect a change in the current by a factor of 10, and this minimum subthreshold slope S puts a fundamental lower limit on the operating voltage and hence the power dissipation in standard FET-based switches. Here, we suggest that by replacing the standard insulator with a ferroelectric insulator of the right thickness it should be possible to implement a step-up voltage transformer that will amplify the gate voltage thus leading to values of S lower than 60 mV/decade and enabling low voltage/low power operation. The voltage transformer action can be understood intuitively as the result of an effective negative capacitance provided by the ferroelectric capacitor that arises from an internal positive feedback that in principle could be obtained from other microscopic mechanisms as well. Unlike other proposals to reduce S, this involves no change in the basic physics of the FET and thus does not affect its current drive or impose other restrictions.

Semiconductor device, and manufacturing method thereof

Abstract: An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.