All existing transistors are based on the use of semiconductor junctions formed by introducing dopant atoms into the semiconductor material. As the distance between junctions in modern devices drops below 10 nm, extraordinarily high doping concentration gradients become necessary. Because of the laws of diffusion and the statistical nature of the distribution of the doping atoms, such junctions represent an increasingly difficult challenge for the semiconductor industry. Here, we propose and demonstrate a new type of transistor in which there are no junctions and no doping concentration gradients. These devices have full CMOS functionality and are made using silicon nanowires. They have near-ideal subthreshold slope, extremely low leakage currents, and less degradation of mobility with gate voltage and temperature than classical transistors.

Nanowire transistors without junctions

Steep subthreshold swing transistors based on interband tunneling are examined toward extending the performance of electronics systems. In particular, this review introduces and summarizes progress in the development of the tunnel field-effect transistors (TFETs) including its origin, current experimental and theoretical performance relative to the metal-oxide-semiconductor field-effect transistor (MOSFET), basic current-transport theory, design tradeoffs, and fundamental challenges. The promise of the TFET is in its ability to provide higher drive current than the MOSFET as supply voltages approach 0.1 V.

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Low-Voltage Tunnel Transistors for Beyond CMOS Logic

Scaling of silicon (Si) transistors is predicted to fail below 5-nanometer (nm) gate lengths because of severe short channel effects. As an alternative to Si, certain layered semiconductors are attractive for their atomically uniform thickness down to a monolayer, lower dielectric constants, larger band gaps, and heavier carrier effective mass. Here, we demonstrate molybdenum disulfide (MoS2) transistors with a 1-nm physical gate length using a single-walled carbon nanotube as the gate electrode. These ultrashort devices exhibit excellent switching characteristics with near ideal subthreshold swing of ~65 millivolts per decade and an On/Off current ratio of ~106 Simulations show an effective channel length of ~3.9 nm in the Off state and ~1 nm in the On state.

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MoS2 transistors with 1-nanometer gate lengths

This paper describes a metal-oxide-semiconductor MOS transistor concept in which there are no junctions. The channel doping is equal in concentration and type to the source and drain extension doping. The proposed device is a thin and narrow multigate field-effect transistor, which can be fully depleted and turned off by the gate. Since this device has no junctions, it has simpler fabrication process, less variability, and better electrical properties than classical MOS devices with source and drain PN junctions.

Junctionless multigate field-effect transistor

For more than four decades, transistors have been shrinking exponentially in size, and therefore the number of transistors in a single microelectronic chip has been increasing exponentially. Such an increase in packing density was made possible by continually shrinking the metal–oxide–semiconductor field-effect transistor (MOSFET). In the current generation of transistors, the transistor dimensions have shrunk to such an extent that the electrical characteristics of the device can be markedly degraded, making it unlikely that the exponential decrease in transistor size can continue. Recently, however, a new generation of MOSFETs, called multigate transistors, has emerged, and this multigate geometry will allow the continuing enhancement of computer performance into the next decade.

Multigate transistors as the future of classical metal–oxide–semiconductor field-effect transistors

This paper describes the simulation of the electrical characteristics of a new transistor concept called the ‘‘Junctionless Multigate Field-Effect Transistor (MuGFET)”. The proposed device has no junctions, a simpler fabrication process, less variability and better electrical properties than classical inversion-mode devices with PN junctions at the source and drain. The simulation results indicate that the junctionless MuGFET is a very promising candidate for future decananometer MOSFET applications.

Performance estimation of junctionless multigate transistors

Conduction mechanisms in junctionless nanowire transistors (gated resistors) are compared to inversion-mode and accumulation-mode MOS devices. The junctionless device uses bulk conduction instead of surface channel. The current drive is controlled by doping concentration and not by gate capacitance. The variation of threshold voltage with physical parameters and intrinsic device performance is analyzed. A scheme is proposed for the fabrication of the devices on bulk silicon.

Junctionless nanowire transistor (JNT): Properties and design guidelines

This paper investigates the temperature dependence of the main electrical parameters of junctionless (JL) silicon nanowire transistors. Direct comparison is made to silicon nanowire (trigate) MOSFETs. Variation of parameters such as threshold voltage and on-off current characteristics is analyzed. The JL silicon nanowire FET has a lager variation of threshold voltage with temperature than the standard inversion- and accumulation-mode FETs. Unlike in classical devices, the drain current of JL FETs increases when temperature is increased.

Chi-Woo Lee

Papers

Nanowire transistors without junctions

Junctionless multigate field-effect transistor

Performance estimation of junctionless multigate transistors

Junctionless nanowire transistor (JNT): Properties and design guidelines

High-Temperature Performance of Silicon Junctionless MOSFETs