Chia-Chun Lin

Bio: Chia-Chun Lin is an academic researcher from National Tsing Hua University. The author has contributed to research in topics: Dielectric & Capacitance. The author has an hindex of 11, co-authored 30 publications receiving 357 citations.

High-performance metal-insulator-metal capacitor with Ge-stabilized tetragonal ZrO2/amorphous La-doped ZrO2 dielectric

Abstract: A Ge-stabilized tetragonal ZrO2 dielectric with a permittivity (κ) value of 36.5 has been obtained by annealing a ZrO2/Ge/ZrO2 laminate at 500 °C and it is a more reliable approach toward stabilizing a tetragonal ZrO2 film. However, metal-insulator-metal (MIM) capacitors with the sole tetragonal ZrO2 film as an insulator achieve a high capacitance density of 27.8 fF/μm2 at the price of a degraded quadratic voltage coefficient of capacitance (VCC) of 81 129 ppm/V2 and unacceptably high leakage current. By capping an amorphous La-doped ZrO2 layer with a κ value of 26.3 to block grain boundaries-induced leakage paths of the crystalline ZrO2 dielectric, high-performance MIM capacitors in terms of a capacitance density of 19.8 fF/μm2, a VCC of 3135 ppm/V2, leakage current of 6.5×10−8 A/cm2 at −1 V, as well as a satisfactory capacitance change of 1.21% after ten-year operation can be realized.

Impact of fluorine treatment on Fermi level depinning for metal/germanium Schottky junctions

Abstract: CF4 plasma treatment on germanium (Ge) surface is proposed in this work to alleviate the strong Fermi level pinning between metal/Ge, and its effectiveness is also explored for n- and p-type Ge wafers. It is found that samples with CF4 plasma treatment reveal conduction behavior transition between Schottky and ohmic characteristics, a metal-work-function-dependent Schottky barrier height as well as modulated contact resistance, and these results confirm the depinning of Fermi level. This depinning can be explained by the effective capability in passivating dangling bonds at Ge surface through fluorine atoms and the formation of Ge-F binding with partial ionic property, both of which are helpful in decreasing the number of surface states and consequently release the pinning effect.

Nonvolatile Memory With Nitrogen-Stabilized Cubic-Phase $\hbox{ZrO}_{2}$ as Charge-Trapping Layer

Abstract: A cubic ZrO2 film formed by annealing of amorphous ZrON has been investigated as the charge-trapping layer for nonvolatile memory. The memory with a nitrogen-stabilized cubic ZrO2 film shows promising performance in terms of 3.81-V hysteresis memory window by ± 7-V program/erase voltage and 1.98-V flatband-voltage shift by programming at +7 V for 10 ms. As compared to that with an amorphous ZrON film, the improved performance is due to the greatly enhanced κ-value of 32.8 and the increased trapping sites provided by grain boundaries. Additionally, it shows 28.6% charge loss after ten-year operation at 85°C. Although it is worse than that with an amorphous ZrON film, it is advantageous over an atomic-layer-depositiongrown tetragonal ZrO2 film in terms of reduced leakage current. Improved retention can be accomplished by passivation of grain boundaries and/or high- κ double quantum barrier as the tunnel and blocking dielectric.

MIM Capacitors With Crystalline- $\hbox{TiO}_{2}/ \hbox{SiO}_{2}$ Stack Featuring High Capacitance Density and Low Voltage Coefficient

Abstract: Metal-insulator-metal (MIM) capacitors with crystalline-TiO2/SiO2 stacked dielectric are explored in this letter. The crystalline TiO2 possesses a high permittivity while the SiO2 provides a negative quadratic voltage coefficient of capacitance (VCC-α) to cancel out the positive VCC-α from the crystalline TiO2. These desirable properties render MIM capacitors with high performance in terms of a capacitance density of 11.9 fF/μm2 with a VCC-α of 90 ppm/V2. With additional N2 plasma treatment on the crystalline TiO2, because of the effective passivation of grain-boundary-related defects and, consequently, a lower leakage current by a factor of 50, the VCC-α can be further lowered to 30 ppm/V2 with slight degradation in capacitance density to 11.2 fF/μm2, which well meets the requirement in 2018 set by ITRS.

Highly stable and efficient all-inorganic lead-free perovskite solar cells with native-oxide passivation.

Abstract: There has been an urgent need to eliminate toxic lead from the prevailing halide perovskite solar cells (PSCs), but the current lead-free PSCs are still plagued with the critical issues of low efficiency and poor stability. This is primarily due to their inadequate photovoltaic properties and chemical stability. Herein we demonstrate the use of the lead-free, all-inorganic cesium tin-germanium triiodide (CsSn0.5Ge0.5I3) solid-solution perovskite as the light absorber in PSCs, delivering promising efficiency of up to 7.11%. More importantly, these PSCs show very high stability, with less than 10% decay in efficiency after 500 h of continuous operation in N2 atmosphere under one-sun illumination. The key to this striking performance of these PSCs is the formation of a full-coverage, stable native-oxide layer, which fully encapsulates and passivates the perovskite surfaces. The native-oxide passivation approach reported here represents an alternate avenue for boosting the efficiency and stability of lead-free PSCs. Replacing the toxic lead in the state-of-the-art halide perovskite solar cells is highly desired but the device performance and stability are usually compromised. Here Chen et al. develop inorganic cesium tin and germanium mixed-cation perovskites that show high operational stability and efficiency over 7%.

Review on Non-Volatile Memory with High-k Dielectrics: Flash for Generation Beyond 32 nm.

Abstract: Flash memory is the most widely used non-volatile memory device nowadays. In order to keep up with the demand for increased memory capacities, flash memory has been continuously scaled to smaller and smaller dimensions. The main benefits of down-scaling cell size and increasing integration are that they enable lower manufacturing cost as well as higher performance. Charge trapping memory is regarded as one of the most promising flash memory technologies as further down-scaling continues. In addition, more and more exploration is investigated with high-k dielectrics implemented in the charge trapping memory. The paper reviews the advanced research status concerning charge trapping memory with high-k dielectrics for the performance improvement. Application of high-k dielectric as charge trapping layer, blocking layer, and tunneling layer is comprehensively discussed accordingly.

Depletion-mode InGaAs metal-oxide-semiconductor field-effect transistor with oxide gate dielectric grown by atomic-layer deposition

Abstract: Recently, significant progress has been made on GaAs metal-oxide-semiconductor field-effect transistors (MOSFETs) using atomic-layer deposition (ALD)-grown Al2O3 as gate dielectric. We show here that further improvement can be achieved by inserting a thin In0.2Ga0.8As layer as part of the channel between Al2O3 and GaAs channel. A 1-μm-gate-length, depletion-mode, n-channel In0.2Ga0.8As/GaAs MOSFET with an Al2O3 gate oxide of 160 A shows a gate leakage current density less than 10−4 A/cm2, a maximum transconductance ∼105 mS/mm, and a strong accumulation current at Vgs>0 in addition to buried-channel conduction. Together with longer gate-length devices, we deduce electron accumulation surface mobility for In0.2Ga0.8As as high as 660 cm2/V s at Al2O3/In0.2Ga0.8As interface.

Germanium surface passivation and atomic layer deposition of high-k dielectrics—a tutorial review on Ge-based MOS capacitors

Abstract: Due to its high intrinsic mobility, germanium (Ge) is a promising candidate as a channel material (offering a mobility gain of approximately??2 for electrons and??4 for holes when compared to conventional Si channels) However, many issues still need to be addressed before Ge can be implemented in high-performance field-effect-transistor (FET) devices One of the key issues is to provide a high-quality interfacial layer, which does not lead to substantial drive current degradation in both low equivalent oxide thickness and short channel regime In recent years, a wide range of materials and processes have been investigated to obtain proper interfacial properties, including different methods for Ge surface passivation, various high-k dielectrics and metal gate materials and deposition methods, and different post-deposition annealing treatments It is observed that each process step can significantly affect the overall metal?oxide?semiconductor (MOS)-FET device performance In this review, we describe and compare combinations of the most commonly used Ge surface passivation methods (eg epi-Si passivation, surface oxidation and/or nitridation, and S-passivation) with various high-k dielectrics In particular, plasma-based processes for surface passivation in combination with plasma-enhanced atomic layer deposition for high-k depositions are shown to result in high-quality MOS structures To further improve properties, the gate stack can be annealed after deposition The effects of annealing temperature and ambient on the electrical properties of the MOS structure are also discussed