Chia-Hung Chen

Bio: Chia-Hung Chen is an academic researcher from National Chiao Tung University. The author has contributed to research in topics: Delta-sigma modulation & Oversampling. The author has an hindex of 10, co-authored 33 publications receiving 307 citations. Previous affiliations of Chia-Hung Chen include Oregon State University & MediaTek.

A Micro-Power Two-Step Incremental Analog-to-Digital Converter

Abstract: Integrated sensor interface circuits require energy-efficient high-resolution data converters. This paper proposes a two-step incremental A/D converter (IADC) which extends the performance of an $N$ th-order IADC close to that of a $(2N-1)$ th-order IADC. The implemented device uses the circuitry of a second-order IADC (IADC2) to achieve close to third-order SNR performance. The proposed circuit does not require very high opamp DC gain; the gain can be as low as 60 dB for 100 dB SNR data conversion. The implemented IADC achieves a measured dynamic range of 99.8 dB, and an SNDR of 91 dB for a maximum input 2.2 V $_{\rm PP}$ and a bandwidth of 250 Hz. Fabricated in 65 nm CMOS, the IADC's core area is 0.2 mm 2 , and it consumes only 10.7 µW. The measured FoMs are 0.76 pJ/conversion and 173.5 dB, both among the best reported results for IADCs. The measured results verify that the proposed two-step IADC is a more energy-efficient data conversion scheme than conventional high-order IADCs.

A 16 b Multi-Step Incremental Analog-to-Digital Converter With Single-Opamp Multi-Slope Extended Counting

Abstract: This paper presents a multi-step incremental analog-to-digital converter (IADC) using multi-slope extended counting. Only one active integrator is used in the three-step conversion cycle. The accuracy of the IADC is extended by having it configured asmulti-slope ADCs in two additional steps. The proposed IADC uses the same circuitry as a first-order IADC (IADC1), but it exhibits better performance than a second-order IADC. For the same accuracy, the conversion cycle is shortened by a large factor (by more than 29 for the implemented device) compared with that of a conventional single-step IADC1. Fabricated in 0.18 $\mu \text{m}$ CMOS process, the prototype ADC occupies 0.5 mm2. With a 642 kHz clock, it achieves an SNDR of 52.2 dB in the first step. The SNDR is boosted to 79.8 dB in the second step and to 96.8 dB in the third step, over a 1 kHz signal band. The power consumption is 35 $\mu \text{W}$ from a 1.5 V power supply. This gives an excellent Schreier figure of merit of 174.6 dB.

A 12-bit 7 µW/channel 1 kHz/channel incremental ADC for biosensor interface circuits

Abstract: A two-channel micro-power incremental ADC, designed for biosensor interface circuits, is reported. It uses a noise-coupled multi-bit delta-sigma loop, integrated with a novel digital decimation filter operating in near-threshold. It was realized in the IBM 90 nm CMOS technology. The fabricated 90nm CMOS prototype device, for a 1 V pp differential input range, experimentally shows a 74dB SNDR up to 2 kHz (1 kHz/channel) signal bandwidth. The total measured power consumption of the modulator is 13.5 µW.

Incremental Delta-Sigma ADCs: A Tutorial Review

Abstract: In many sensor applications, a high-resolution analog-to-digital converter (ADC) is a key block. The use of an incremental delta-sigma ADC (IADC) is often well suited for such applications. While the energy-efficiency of IADCs has improved by several orders of magnitude over the past decade, the implementation of high performance IADCs, especially in battery-powered systems, is still challenging. This paper presents a tutorial review on energy-efficient IADCs and addresses the progress in this area. This paper describes the fundamentals of IADCs and energy-efficient hybrid IADC architectures. Various design techniques for improving the energy-efficiency of the IADCs are described. This paper is intended to serve as a starting point for the development of a new energy-efficient IADC.

A Continuous-Time Delta-Sigma Modulator for Biomedical Ultrasound Beamformer Using Digital ELD Compensation and FIR Feedback

Abstract: This paper presents the design of a continuous-time $\Delta\Sigma$ modulator (CTDSM) to be used in an ultrasound beamformer for biomedical imaging. To achieve better resolution, the prototype modulator operates at 1.2 GHz. It incorporates a digital excess loop delay (ELD) compensation to replace the active adder in front of the internal quantizer. A digitally controlled reference-switching matrix, combined with the data-weighted averaging (DWA) technique, results in a delay-free feedback path. A multi-bit FIR feedback DAC, along with its compensation path, is used to achieve lower clock jitter sensitivity and better loop filter linearity. The modulator achieves 79.4 dB dynamic range, 77.3 dB SNR, and 74.3 dB SNDR over a 15 MHz signal bandwidth. Fabricated in a 65 nm CMOS process, the core modulator occupies an area of only 0.16 ${\rm mm}^{2}$ and dissipates 6.96 mW from a 1 V supply. A 58.6 fJ/conversion-step figure of merit is achieved.

Neural-like computing with populations of superparamagnetic basis functions.

Abstract: In neuroscience, population coding theory demonstrates that neural assemblies can achieve fault-tolerant information processing. Mapped to nanoelectronics, this strategy could allow for reliable computing with scaled-down, noisy, imperfect devices. Doing so requires that the population components form a set of basis functions in terms of their response functions to inputs, offering a physical substrate for computing. Such a population can be implemented with CMOS technology, but the corresponding circuits have high area or energy requirements. Here, we show that nanoscale magnetic tunnel junctions can instead be assembled to meet these requirements. We demonstrate experimentally that a population of nine junctions can implement a basis set of functions, providing the data to achieve, for example, the generation of cursive letters. We design hybrid magnetic-CMOS systems based on interlinked populations of junctions and show that they can learn to realize non-linear variability-resilient transformations with a low imprint area and low power.

Materials Strategies and Device Architectures of Emerging Power Supply Devices for Implantable Bioelectronics

Abstract: Implantable bioelectronics represent an emerging technology that can be integrated into the human body for diagnostic and therapeutic functions. Power supply devices are an essential component of bioelectronics to ensure their robust performance. However, conventional power sources are usually bulky, rigid, and potentially contain hazardous constituent materials. The fact that biological organisms are soft, curvilinear, and have limited accommodation space poses new challenges for power supply systems to minimize the interface mismatch and still offer sufficient power to meet clinical-grade applications. Here, recent advances in state-of-the-art nonconventional power options for implantable electronics, specifically, miniaturized, flexible, or biodegradable power systems are reviewed. Material strategies and architectural design of a broad array of power devices are discussed, including energy storage systems (batteries and supercapacitors), power devices which harvest sources from the human body (biofuel cells, devices utilizing biopotentials, piezoelectric harvesters, triboelectric devices, and thermoelectric devices), and energy transfer devices which utilize sources in the surrounding environment (ultrasonic energy harvesters, inductive coupling/radiofrequency energy harvesters, and photovoltaic devices). Finally, future challenges and perspectives are given.

Neural-like computing with populations of superparamagnetic basis functions

Abstract: In neuroscience, population coding theory demonstrates that neural assemblies can achieve fault-tolerant information processing. Mapped to nanoelectronics, this strategy could allow for reliable computing with scaled-down, noisy, imperfect devices. Doing so requires that the population components form a set of basis functions in terms of their response functions to inputs, offering a physical substrate for calculating. For this purpose, the responses of the nanodevices should be non-linear, and each tuned to different values of the input. These strong requirements have prevented a demonstration of population coding with nanodevices. Here, we show that nanoscale magnetic tunnel junctions can be assembled to meet these requirements. We demonstrate experimentally that a population of nine junctions can implement a basis set of functions, providing the data to achieve, for example, the generation of cursive letters. We design hybrid magnetic-CMOS systems based on interlinked populations of junctions and show that they can learn to realize non-linear variability-resilient transformations with a low imprint area and low power.

Next-Generation Delta-Sigma Converters: Trends and Perspectives

Abstract: This paper presents an overview of emerging circuits and systems techniques which are at the forefront of the state of the art in $\Delta\Sigma$ modulators, pushing their performance forward and giving rise to new generations of data converters. Among others, those strategies involving the development of new applications and paradigms—like RF/GHz-range $\Delta\Sigma$ digitisation, digital-assisted embedded loop filters, time-to-digital conversion and hybrid $\Delta\Sigma$ /Nyquist-rate architectures—are discussed, as well as the implications and design challenges derived from their integration in deep nanometer CMOS technologies. The envisioned $\Delta\Sigma$ techniques are presented in a systematic way around the main analog building blocks embedded in a $\Delta\Sigma$ modulator, i.e., the loop filter and the quantizer. Analysing the trends in the design of these blocks allows us to offer perspectives on how $\Delta\Sigma$ converters will evolve in the next years.

A Highly Digital VCO-Based ADC Architecture for Current Sensing Applications

Abstract: This paper presents a voltage-controlled oscillator (VCO) based current to digital converter for sensor readout applications. Second order noise shaping of the quantization error is achieved by using implicit capacitance of the sensor to realize a passive integrator and a VCO-based quantizer. The non-linearity in voltage to frequency conversion of the VCO is tackled by placing the VCO in a loop consisting of a simple digital IIR filter and a passive integrator. The IIR filter provides large gain within the signal bandwidth and suppresses VCO input swing. As a result, non-linearity of the VCO is not exercised, thus greatly improving the proposed architecture's immunity to VCO nonlinearity. The use of a digital filter instead of an analog loop filter eases the design and makes it scaling friendly. Designed for an ambient light sensor application, the proposed circuit achieves 900 pA accuracy over an input current range of 4 $\mu$ A. Fabricated in a 0.18 $\mu$ m CMOS process, the readout circuit consumes a total of 77.8 $\mu$ A current, and occupies an active area of 0.36 mm $^2$ .