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Chih-Tung Chen

Other affiliations: Freescale Semiconductor
Bio: Chih-Tung Chen is an academic researcher from Motorola. The author has contributed to research in topics: High-level synthesis & Power optimization. The author has an hindex of 6, co-authored 10 publications receiving 145 citations. Previous affiliations of Chih-Tung Chen include Freescale Semiconductor.

Papers
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Patent
29 May 1998
TL;DR: A customizable instruction-set processor (10) as mentioned in this paper implements complex, time-consuming operations by reconfiguring a portion of an instruction execution unit (34) to perform a group of specific functions in hardware rather than implementing a string of operations in software routines.
Abstract: A customizable instruction-set processor (10) implements complex, time-consuming operations by reconfiguring a portion of an instruction execution unit (34) to perform a group of specific functions in hardware rather than implementing a string of operations in software routines. The instruction execution unit (34) has a non-programmable section (46) and a programmable section (48) that receive an opcode and output control signals for controlling a datapath (16). The datapath (16) has a non-programmable datapath (18) and a programmable datapath (32). The programmable section (48) and the programmable datapath (32) are programmed by the user to provide a customizable instruction-set that controls and adds functionality to the customizable instruction-set processor (10).

46 citations

Patent
24 Feb 1997
TL;DR: In this article, a system is dynamically characterized by annotating an RTL component (step 153) and simulating the system over a range of simulation cycles, where states at selectable simulation cycles are displayed in different orders and at multiple architectural levels.
Abstract: A method (30) and apparatus (300) for characterizing the operation of an architectural system designed through a plurality of design tasks (102-112). The design tasks are associated with architectural design rules (114-124) that compare a mapping of the system to a set of rules which are indicative of an error-free system. Objects in the mapping that do not conform to the architectural rules are identified and can be displayed at multiple architectural levels through one or more editors (26-28) and modified without leaving the editors. The system is dynamically characterized by annotating an RTL component (step 153) and simulating the system over a range of simulation cycles. The annotated component (130) monitors states of the system for storing in an analysis database (24). States at selectable simulation cycles are displayed in different orders and at multiple architectural levels.

28 citations

Journal ArticleDOI
TL;DR: Matisse is an architectural design tool that increases productivity without sacrificing area, performance, or power and supports the diverse design practices required for commodity IC design by giving the designer fine-grain control of behavioral synthesis tasks.
Abstract: To accelerate industrial adoption of behavioral synthesis, we have developed Matisse, an architectural design tool that increases productivity without sacrificing area, performance, or power. Matisse's main difference from traditional behavioral synthesis tools is that it lets the designer play a key role. It allows the designer to make major decisions about styles, protocols, parallelism, delays, and partial or even complete architectures before the behavioral synthesis phase starts. Then it enables the designer to incorporate these decisions into the architecture using behavioral synthesis. Matisse supports the diverse design practices required for commodity IC design by giving the designer fine-grain control of behavioral synthesis tasks.

27 citations

Patent
03 Dec 1996
TL;DR: In this article, a register transfer logic (RTL) implementation of an integrated circuit is generated by performing a set of design tasks, which can be modified by branching to another design task such that the design tasks are performed in any order.
Abstract: A computer implemented architectural design method for designing an integrated circuit. An algorithmic description of the behavior of the integrated circuit is created (step 202), from which a register transfer logic (RTL) implementation (400, 500) of the integrated circuit is generated by performing a set of design tasks (steps 204-212). The RTL implementation is modified after performing one of the design tasks by branching to another design task such that the design tasks are performed in any order. Data is stored in a common database (12) which can be edited interactively through one of a plurality of data editors (14-22).

18 citations

Proceedings ArticleDOI
12 Oct 1997
TL;DR: An environment for exploring low-power architectures using high-level synthesis, which is currently being used for production chip design until comprehensive commercialized alternatives are available is described.
Abstract: Architectural power optimization offers significant power gains in addition to which can be obtained at higher and lower levels of abstraction. Although there has been some academic research for architectural power optimization, the commercial design automation technology is still in infancy and quite behind the current needs of the industry as many portable computing and communication products and greener non-portable products are being introduced into the market. In this paper we describe an environment for exploring low-power architectures using high-level synthesis, which is currently being used for production chip design until comprehensive commercialized alternatives are available. We also present the results and findings from experiments with a CCITT G.721 ADPCM Predictor design, which should benefit on-going research on automated solutions.

9 citations


Cited by
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Journal ArticleDOI
Jason Cong, Bin Liu, Stephen Neuendorffer1, Juanjo Noguera1, Kees Vissers1, Zhiru Zhang 
TL;DR: AutoESL's AutoPilot HLS tool coupled with domain-specific system-level implementation platforms developed by Xilinx are used as an example to demonstrate the effectiveness of state-of-art C-to-FPGA synthesis solutions targeting multiple application domains.
Abstract: Escalating system-on-chip design complexity is pushing the design community to raise the level of abstraction beyond register transfer level. Despite the unsuccessful adoptions of early generations of commercial high-level synthesis (HLS) systems, we believe that the tipping point for transitioning to HLS msystem-on-chip design complexityethodology is happening now, especially for field-programmable gate array (FPGA) designs. The latest generation of HLS tools has made significant progress in providing wide language coverage and robust compilation technology, platform-based modeling, advancement in core HLS algorithms, and a domain-specific approach. In this paper, we use AutoESL's AutoPilot HLS tool coupled with domain-specific system-level implementation platforms developed by Xilinx as an example to demonstrate the effectiveness of state-of-art C-to-FPGA synthesis solutions targeting multiple application domains. Complex industrial designs targeting Xilinx FPGAs are also presented as case studies, including comparison of HLS solutions versus optimized manual designs. In particular, the experiment on a sphere decoder shows that the HLS solution can achieve an 11-31% reduction in FPGA resource usage with improved design productivity compared to hand-coded design.

728 citations

Patent
12 Jan 1999
TL;DR: In this paper, a multithread HDL logic simulator that can process both VHDL and Verilog languages in a single program is described, and it uses special concurrent algorithms to accelerate the tool's performance on multiprocessor platforms to achieve linear to super-linear scalability.
Abstract: This invention describes a multithread HDL logic simulator that is unique from the prior arts. Specifically, it can process both VHDL and Verilog languages in a single program, and it uses special concurrent algorithms to accelerate the tool's performance on multiprocessor platforms to achieve linear to super-linear scalability on multiprocessor systems. Furthermore, the invention includes a unique remote logic simulation and job scheduling capabilities.

222 citations

Patent
04 Feb 2003
TL;DR: In this article, a method for compiling a logic design is presented, where the logic design comprises a plurality of modules, compiling separately the plurality of module files into object files, and linking the plurality files to execute the logic.
Abstract: A method for compiling a logic design includes inputting a logic design and an input file into a plurality of compilers, respectively, where the logic design comprises a plurality of modules, compiling separately the plurality of modules into a plurality of object files, and linking the plurality of object files to execute the logic design.

132 citations

Patent
24 Jul 1998
TL;DR: Register transfer level (RTL) source code is synthesized to generate a gate-level representation and to generate instrumentation logic corresponding to one or more statements in the RTL source code as discussed by the authors.
Abstract: Register transfer level (RTL) source code is synthesized to generate a gate-level representation and to generate instrumentation logic corresponding to one or more statements in the RTL source code. The instrumentation logic comprises logic circuitry in addition to that of the gate-level representation. The instrumentation logic indicates an execution status for the corresponding RTL statement(s) during gate-level simulation.

73 citations

Patent
06 Feb 2002
TL;DR: In this paper, a VLIW processor design system automates the design of programmable and non-programmable VAE processors by taking as input an opcode repertoire, the I/O format of the opcodes, a register file specification, and instruction-level parallelism constraints.
Abstract: A VLIW processor design system automates the design of programmable and non-programmable VLIW processors. The system takes as input an opcode repertoire, the I/O format of the opcodes, a register file specification, and instruction-level parallelism constraints. With this input specification, the system constructs a datapath, including functional units, register files and their interconnect components from a macrocell database. The system uses the input and the datapath to generate an instruction format design. The instruction format may then be used to construct the processor control path. The abstract input and datapath may be used to extract a machine description suitable to re-target a compiler to the processor. To optimize the processor for a particular application program, the system selects custom instruction templates based on operation issue statistics for the application program generated by the re-targeted compiler.

67 citations