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Chin-Li Kao

Bio: Chin-Li Kao is an academic researcher. The author has contributed to research in topics: Materials science & Scanning electron microscope. The author has an hindex of 5, co-authored 5 publications receiving 194 citations.

Papers
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Journal ArticleDOI
TL;DR: The support excitation scheme incorporated with the implicit time integration scheme is implemented to study transient structural responses of a board-level chip-scale package subjected to consecutive drops and accumulated stresses, plastic strains, and plastic strain energy densities on the solder joints under repetitive drop impacts are investigated.

71 citations

Journal ArticleDOI
TL;DR: The finite element analysis is performed to investigate characteristics of current crowding in a flip-chip solder bump subjected to a constant applied current and it is found that under such a condition,Current crowding is induced solely by the structural geometry of the system.

55 citations

Journal ArticleDOI
TL;DR: In this article, a numerical analysis of pull test reliability of gold wires bonded on the Cu/low-K wafer was performed to allocate residual stresses within the wire and the structure.
Abstract: This paper focuses on the numerical analysis of pull test reliability of gold wires bonded on the Cu/low-K wafer. Prior to wire pull, transient analysis of the complete wirebonding process, which involves both impact and ultrasonic vibration stages, is performed to allocate residual stresses within the wire and the Cu/low-K structure. After wirebonding, fracturing of the wire subjected to a pull load is modeled using the eroding technique so that failure patterns and bonding strength of the wire can be investigated. The analysis applies the explicit time integration scheme, which is feasible in dealing with nonlinear transient structural behavior. Parametric studies show that as the yield stress of the low-K material decreases, the pull force reduces significantly. Furthermore, the pull force increases as the bond force increases but not very significantly

33 citations

Patent
13 Nov 2014
TL;DR: In this article, the authors present a semiconductor package with a main body, a plurality of conductive vias, and at least one filler, where the filler is located in the main body.
Abstract: The present disclosure relates to a semiconductor package and a manufacturing method thereof The semiconductor package includes a semiconductor element including a main body, a plurality of conductive vias, and at least one filler. The conductive vias penetrate through the main body. The filler is located in the main body, and a coefficient of thermal expansion (CTE) of the filler is different from that of the main body and the conductive vias. Thus, the CTE of the overall semiconductor element can be adjusted, so as to reduce warpage.

20 citations

Proceedings ArticleDOI
07 Dec 2005
TL;DR: In this article, a numerical methodology based on the support excitation scheme and incorporated with the implicit time integration scheme was used to investigate the transient structural responses of a board-level chip-scale package subjected to consecutive drops.
Abstract: Transient structural responses of a board-level chip-scale package subjected to consecutive drops are investigated in this paper using a numerical methodology based on the support excitation scheme and incorporated with the implicit time integration scheme. Evolutions of stresses, plastic strains, and plastic strain energies in the solder joints under repetitive drop impacts are examined and correlated with actual experimental observations. Effects of isotropic hardening and kinematic hardening presumed for the solder alloy are examined and compared

20 citations


Cited by
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Journal ArticleDOI
TL;DR: In this article, the authors review the unique features of EM and TM in flip-chip solder bumps, emphasizing the effects of current crowding and Joule heating on the dissolution rates of Ni and Cu.
Abstract: Pb-free solders have replaced Pb-containing SnPb solders in the electronic packaging industry due to environmental concerns. Both electromigration (EM) and thermomigration (TM) have serious reliability issues for fine-pitch Pb-free solder bumps in the flip-chip technology used in consumer electronic products. We review the unique features of EM and TM in flip-chip solder bumps, emphasizing the effects of current crowding and Joule heating. In addition, the challenges to a better understanding of EM and TM in Pb-free solders are discussed. For example, the anisotropic nature of Sn microstructure in Pb-free solders can enhance the dissolution rates of Ni and Cu in solders driven by EM and TM.

250 citations

Journal ArticleDOI
TL;DR: This paper reviews the research progress on the reliability of lead-free solder joints and discusses the influence of temperature, vibration, tin whisker and electromigration onThe reliability of solder joints.

90 citations

Journal ArticleDOI
TL;DR: A number of solutions to the problems and recent findings/developments related to wire bonding using copper wire or insulated wire are discussed.

87 citations

Journal ArticleDOI
TL;DR: The electrothermal coupling analysis was employed to investigate the current crowding effect and maximum temperature in the solder bump in order to correlate with the experimental electromigration reliability using the Black’s equation as a reliability model.

73 citations

Proceedings ArticleDOI
25 Jun 2007
TL;DR: In this paper, a non-contact optical technique has been proposed for measurement of full-field impact response using a pair of synchronized high-speed cameras captured the images of board assembly subjected to JEDEC standard impact, at rates up to 15,000 pictures per second.
Abstract: Product durability due to drop shock is a critical element for assessment of reliability for handheld devices. So far, no simulation model for a board-level drop has been extensively validated by experiments for its predictions of global (full-field) dynamic response. Accelerometers and strain gages which are traditionally utilized to measure the response at selected locations, fail to assess the global strain gradients and complex mode shapes. In this work, a novel non-contact optical technique has been proposed for measurement of full-field impact response. Pair of synchronized high-speed cameras capture the images of board assembly subjected to JEDEC standard impact, at rates up to 15,000 pictures per second. A digital image correlation (DIC) system has been integrated with the cameras to analyze the acquired images to give dynamic deformation, shape and strain over the entire surface of board during impact. A finite element model for the drop test has been developed using ANSYS/LS-DYNA. The numerical solution has been fully validated against experimental measurements of acceleration, strain and warpage at series of instants of time after impact. Effect of tightening torque at PCB mounts has been studied comprehensively with regards to the eigenvalues and mode shapes, and the necessity for accurate modeling of dynamic contact conditions existing at the supports has been demonstrated. Simulation model has been further used to assess the drop impact reliability of components on the board. Excellent correlation of all simulation results with the measured data validates the experimental and numerical propositions made in this work for analyzing a board-level drop impact.

68 citations