Chin-Tang Sah

Bio: Chin-Tang Sah is an academic researcher from University of Florida. The author has contributed to research in topics: Charge carrier & Semiconductor. The author has an hindex of 3, co-authored 4 publications receiving 454 citations.

Fundamentals of Solid State Electronics

Abstract: Electrons, bonds, bands and holes homogeneous semiconductor at equilibrium drift, diffusion, generation, recombination, trapping and tunneling metal-oxide-semiconductor capacitor P/N and other junction diodes metal-oxide-semiconductor and other field-effect transistors bipolar junction transistor and other bipolar transistor devices.

Oxide charge induced high low junction emitter solar cell

Abstract: A high-low junction emitter silicon solar cell including an electron accumulation layer formed by oxide-charge-induction.

TDCIV extraction of dopant-impurity concentration and oxide thickness in ultrathin gate oxide MOS transistors

Abstract: A methodology is demonstrated for lateral position profiling of surface dopant-impurity concentration in the channel region and two extension regions using experimental tunnel direct-current current-voltage (TDCIV) curves on a pMOS transistor with W/L = 10/spl mu/m/0.3/spl mu/m fabricated by a factory 100nm technology. The methodology employs a zeroth-order and a first-order TDCIV model. Based on the zeroth-order model, constant oxide thickness, constant surface substrate-dopant-impurity concentration, and region length in each region were extracted. Then, using lateral dopant-impurity profile formulae in the first-order model to fit the TDCIV drain, source and basewell current data, the spatial variations of surface dopant-impurity concentration in the three regions are obtained.

Fundamentals of Modern VLSI Devices

Abstract: Learn the basic properties and designs of modern VLSI devices, as well as the factors affecting performance, with this thoroughly updated second edition. The first edition has been widely adopted as a standard textbook in microelectronics in many major US universities and worldwide. The internationally-renowned authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices. Equations and parameters provided are checked continuously against the reality of silicon data, making the book equally useful in practical transistor design and in the classroom. Every chapter has been updated to include the latest developments, such as MOSFET scale length theory, high-field transport model, and SiGe-base bipolar devices.

Overview of nanoelectronic devices

Abstract: This paper provides an overview of research developments toward nanometer-scale electronic switching devices for use in building ultra-densely integrated electronic computers. Specifically, two classes of alternatives to the field-effect transistor are considered: (1) quantum-effect and single-electron solid-state devices and (2) molecular electronic devices. A taxonomy of devices in each class is provided, operational principles are described and compared for the various types of devices, and the literature about each is surveyed. This information is presented in nonmathematical terms intended for a general, technically interested readership.

MOS Scaling: Transistor Challenges for the 21st Century

Abstract: Conventional scaling of gate oxide thickness, source/drain extension (SDE), junction depths, and gate lengths have enabled MOS gate dimensions to be reduced from 10μm in the 1970’s to a present day size of 0.1μm. To enable transistor scaling into the 21 century, new solutions such as high dielectric constant materials for gate insulation and shallow, ultra low resistivity junctions need to be developed. In this paper, for the first time, key scaling limits are quantified for MOS transistors (see Table 1). We show that traditional SiO2 gate dielectrics will reach fundamental leakage limits, due to tunneling, for an effective electrical thickness below 2.3 nm. Experimental data and simulations are used to show that although conventional scaling of junction depths is still possible, increased resistance for junction depths below 30 nm results in performance degradation. Because of these limits, it will not be possible to further improve short channel effects. This will result in either unacceptable off-state leakage currents or strongly degraded device performance for gate lengths below 0.10μm. MOS transistor limits will be reached for 0.13μm process technologies in production during 2002. Because of these problems, new solutions will need to be developed for continued transistor scaling. We discuss some of the proposed solutions including high dielectric constant gate materials and alternate device architectures.

Characteristics of the metal-Oxide-semiconductor transistors

Abstract: The theory of the MOS transistor in the gradual channel approximation is presented with the assumption of constant surface and bulk charge, and constant surface mobility. From the simple theory, the complete design equations are derived and design curves are calculated. From the analysis, the equivalent circuit parameters of the device are related to the basic properties of the material and geometry of the device. The simple theory is then critically compared with experimental measurements of MOS transistors with circular geometry. The comparison shows good general agreement with the theory of the dc characteristics but discrepancies are found for the differential characteristics such as the transconductance and the gate capacitance. The possible sources of the discrepancies are discussed.