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Ching-Ji Huang

Bio: Ching-Ji Huang is an academic researcher from Industrial Technology Research Institute. The author has contributed to research in topics: System on a chip & Logic level. The author has an hindex of 2, co-authored 4 publications receiving 99 citations.

Papers
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Journal ArticleDOI
TL;DR: A novel level shifter, of which the operating range is from a deep subthreshold voltage to the standard supply voltage and includes upward and downward level conversion and is designed for practical applications.
Abstract: Wide-range level shifters play critical roles in ultra- low-voltage circuits and systems. Although state-of-the-art level shifters can convert a subthreshold voltage to the standard supply voltage, they may have limited operating ranges, which restrict the flexibility of dynamic voltage scaling. Therefore, this paper presents a novel level shifter, of which the operating range is from a deep subthreshold voltage to the standard supply voltage and includes upward and downward level conversion. The proposed level shifter is a hybrid structure comprising a modified Wilson current mirror and generic CMOS logic gates. The simulation and measurement results were verified using a 65-nm technology. The minimal operating voltage of the proposed level shifter was less than 200 mV based on the measurement results. In addition to the operating range, the delay, power consumption, and duty cycle of the proposed level shifter were designed for practical applications.

105 citations

Journal ArticleDOI
TL;DR: This brief proposes an adaptive pulse-generating method to fit the transparent window required in situ to improve the robustness of pulse-triggered flip-flops and promises this high-speed clocked element for wide-voltage-range operations.
Abstract: Pulse-triggered flip-flops are candidates to improve pipeline speed, although flip-flop robustness and system timing closure are challenging in a wide range of supply voltages. Pulse-triggered flip-flops usually have specific structures and transistor sizes to optimize performance. The topology, transistor size, and threshold voltage of the flip-flop make the timing characteristics sensitive to the supply voltage. The transparent windows generated and required in a pulse-triggered flip-flop may have mismatch under supply voltage scaling, which is likely to result in functional and system timing failures. Therefore, this brief proposes an adaptive pulse-generating method to fit the transparent window required in situ. Process variations and intrinsic transistor driving-strength mismatches are considered. The proposed structure improves the robustness of pulse-triggered flip-flops and promises this high-speed clocked element for wide-voltage-range operations. A normalized timing metric is also introduced to characterize flip-flops and help timing tradeoffs in wide-voltage-range operations.

18 citations

Proceedings ArticleDOI
16 Apr 2018
TL;DR: An energy-scalable computing platform for flexible and smart WSN edge applications that comprises a 32-bit OpenRISC processor and two 4KB instruction and data caches on a chip, which can be operated in a wide supply voltage range.
Abstract: This paper presents an energy-scalable computing platform for flexible and smart WSN edge applications. The platform comprises a 32-bit OpenRISC processor and two 4KB instruction and data caches on a chip, which can be operated in a wide supply voltage range. Adaptive voltage scaling makes this processor search its minimal operating voltage given a performance prerequisite. Different from many embedded MCU platforms, DRAM is supported here to expend flexibility of programing and data logging. This system on a chip (SoC) was implemented using TSMC 0.18 μm CMOS process, the operating range is from 0.6V, 2.5MHz to 1.2V, 40MHz. Measurements show the SoC achieves 170μW/MHz at 0.6V, offering a cost- and energy-efficient edge design solution.

2 citations

Journal ArticleDOI
TL;DR: An implementation of ultralow-power microcontrollers that use a separate clock network voltage (SCNV) to correct unexpected errors produced by on-chip variations (OCVs) is presented and proper applications are discussed.
Abstract: This brief presents an implementation of ultralow-power microcontrollers that use a separate clock network voltage (SCNV) to correct unexpected errors produced by on-chip variations (OCVs). Separating the clock network voltage requires amendments in the standard cell library and physical designs. Here, the experiments used a 65-nm technology that exhibited considerable OCVs, which caused write and retention errors in clocked storage cells and limited the voltage scaling of microcontrollers. Using the SCNV provides an extraordinary operability to correct errors in the low-voltage clocked storage cells. In addition, the area overhead of the proposed implementation is negligible. Applying the SCNV, the measurement results indicate that the microcontrollers can be operated below 0.3 V, over 0.15-V extension in voltage scaling, and achieve the optimal energy consumption at 0.34 V. Separating the clock network voltage has tradeoff issues in system timing and energy consumption based on the measurement results, and this brief discusses proper applications.

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Journal ArticleDOI
TL;DR: A novel ultra-low voltage level shifter for fast and energy-efficient wide-range voltage conversion from sub-threshold to I/O voltage with good delay scalability with supply voltage scaling and low sensitivity to process and temperature variations is presented.
Abstract: This paper presents a novel ultra-low voltage level shifter for fast and energy-efficient wide-range voltage conversion from sub-threshold to I/O voltage. By addressing the voltage drop and non-optimal feedback control in a state-of-the-art level shifter based on Wilson current mirror, the proposed level shifter with revised Wilson current mirror significantly improves the delay and power consumption while achieving a wide voltage conversion range. It also employs mixed-Vt device and device sizing aware of inverse narrow width effect to further improve the delay and power consumption. Measurement results at 0.18 μm show that compared with the Wilson current mirror based level shifter, the proposed level shifter improves the delay, switching energy and leakage power by up to 3×, 19×, 29× respectively, when converting 0.3 V to a voltage between 0.6 V and 3.3 V. More specifically, it achieves 1.03 (or 1.15) FO4 delay, 39 (or 954) fJ/transition and 160 (or 970) pW leakage power, when converting 0.3 V to 1.8 V (or 3.3 V), which is better than several state-of-the-art level shifters for similar range voltage conversion. The measurement results also show that the proposed level shifter has good delay scalability with supply voltage scaling and low sensitivity to process and temperature variations.

82 citations

Journal ArticleDOI
TL;DR: An energy-efficient level shifter able to convert extremely low level input voltages to the nominal voltage domain based on the single-stage differential-cascode-voltage-switch scheme that exploits self-adapting pull-up networks to increase the switching speed and to reduce the dynamic energy consumption.
Abstract: This brief presents an energy-efficient level shifter (LS) able to convert extremely low level input voltages to the nominal voltage domain. To obtain low static power consumption, the proposed architecture is based on the single-stage differential-cascode-voltage-switch scheme. Moreover, it exploits self-adapting pull-up networks to increase the switching speed and to reduce the dynamic energy consumption, while a split input inverting buffer is used as the output stage to further improve energy efficiency. When implemented in a commercial 180-nm CMOS process, the proposed design can up-convert from the deep subthreshold regime (sub-100 mV) to the nominal supply voltage (1.8 V). For the target voltage level conversion from 0.4 to 1.8 V, our LS exhibits an average propagation delay of 31.7 ns, an average static power of less than 60 pW, and an energy per transition of 173 fJ, as experimentally measured across the test chips.

73 citations

Journal ArticleDOI
TL;DR: The proposed PUF exploits the intrinsic imperfection during the image sensor manufacturing process to generate unique and reliable digital signatures and stabilizes the response bits extracted from the random fixed pattern noises of selected pixel pairs determined by the applied challenge against supply voltage and temperature variations.
Abstract: In the applications of biometric authentication and video surveillance, the image sensor is expected to provide certain degree of trust and resiliency. This paper presents a new low-cost CMOS image sensor based physical unclonable function (PUF) targeting a variety of security, privacy and trusted protocols that involves image sensor as a trusted entity. The proposed PUF exploits the intrinsic imperfection during the image sensor manufacturing process to generate unique and reliable digital signatures. The proposed differential readout stabilizes the response bits extracted from the random fixed pattern noises of selected pixel pairs determined by the applied challenge against supply voltage and temperature variations. The threshold of difference can be tightened to winnow out more unstable response bits from the challenge-response space offered by modern image sensors to enhance the reliability under harsher operating conditions and loosened to improve its resiliency against masquerade attacks in routine operating environment. The proposed design can be classified as a weak PUF which is resilient to modeling attacks, with direct access to its challenge-response pair restricted by the linear feedback shift register. Our experiments on the reset voltages extracted from a 64 $\times$ 64 image sensor fabricated in 180 nm 3.3 V CMOS technology demonstrated that robust and reliable challenge-response pairs can be generated with a uniqueness of 49.37% and a reliability of 99.80% under temperature variations of $15\sim 115~^{\circ}{\rm C}$ and supply voltage variations of $3\sim 3.6\ {\rm V}$ .

71 citations

Journal ArticleDOI
TL;DR: In this article, a mixed TFET-MOSFET level shifter (LS) for voltage up-conversion from the ultralow-voltage regime is proposed.
Abstract: In this paper, we identify the level shifter (LS) for voltage up-conversion from the ultralow-voltage regime as a key application domain of tunnel FETs (TFETs). We propose a mixed TFET–MOSFET LS design methodology, which exploits the complementary characteristics of TFET and MOSFET devices. Simulation results show that the hybrid LS exhibits superior dynamic performance at the same static power consumption compared with the conventional MOSFET and pure TFET solutions. The advantage of the mixed design with respect to the conventional MOSFET approach is emphasized when lower voltage signals have to be up-converted, reaching an improvement of the energy-delay product up to three decades. When compared with the full MOSFET design, the mixed TFET–MOSFET solution appears to be less sensitive toward threshold voltage variations in terms of dynamic figures of merit, at the expense of higher leakage variability. Similar results are obtained for four different LS topologies, thus indicating that the hybrid TFET–MOSFET approach offers intrinsic advantages in the design of LS for voltage up-conversion from the ultralow-voltage regime compared with the conventional MOSFET and pure TFET solutions.

63 citations

Journal ArticleDOI
TL;DR: This brief introduces a novel LS circuit with NMOS-diode-based current limiter for current contention reduction to achieve robust and efficient level conversion and explores the inverse narrow width effect to increase the drivability of the pull-down devices for delay reduction.
Abstract: Level shifters (LS) are crucial interface circuits for multisupply voltage designs, and it is challenging to achieve both robust and efficient level conversion from subthreshold to aforementioned threshold. In this brief, we propose two circuit techniques for a novel subthreshold LS with wide conversion range. First, we introduce a novel LS circuit with NMOS-diode-based current limiter for current contention reduction to achieve robust and efficient level conversion. Second, we explore the inverse narrow width effect to increase the drivability of the pull-down devices for delay reduction. When implemented in a commercial 65-nm MTCMOS process, the proposed LS achieves robust conversion from deep subthreshold (sub-100 mV) to nominal supply voltage (1.2 V). For the target conversion from 0.3 to 1.2 V, the proposed LS shows on average 25.1-ns propagation delay, 30.7-fJ energy efficiency, and 2.5-nW leakage power across 25 test chips.

59 citations