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Design Of Integrated Circuits For Optical Communications

Receivers, which may be external or implantable, are provided. Aspects of receivers of the invention include the presence of one or more of: a high power-low power module; an intermediary module; a power supply module configured to activate and deactivate one or more power supplies to a high power processing block; a serial peripheral interface bus connecting master and slave blocks; and a multi-purpose connector. Receivers of the invention may be configured to receive a conductively transmitted signal. Also provided are systems that include the receivers, as well as methods of using the same. Additionally systems and methods are disclosed for using a receiver for coordinating with dosage delivery systems.

Body-associated receiver and method

The adoption of dynamic dividers in CMOS phase-locked loops for multigigahertz applications allows to reduce the power consumption substantially without impairing the phase noise and the power supply sensitivity of the phase-locked loop (PLL). A 5-GHz frequency synthesizer integrated in a 0.25-/spl mu/m CMOS technology demonstrates a total power consumption of 13.5 mW. The frequency divider combines the conventional and the extended true-single-phase-clock logics. The oscillator employs a rail-to-rail topology in order to ensure a proper divider function. This PLL intended for wireless LAN applications can synthesize frequencies between 5.14 and 5.70 GHz in steps of 20 MHz. The reference spurs at 10-MHz offset are as low as -70 dBc and the phase noise is lower than -116 dBc/Hz at 1 MHz over the whole tuning range.

A 13.5-mW 5-GHz frequency synthesizer with dynamic-logic frequency divider

Radio frequency integrated circuits (RFICs) are the building blocks that enable every device from cable television sets to mobile telephones to transmit and receive signals and data. This newly revised and expanded edition of the 2003 Artech House classic, "Radio Frequency Integrated Circuit Design", serves as an up-to-date, practical reference for complete RFIC know-how. The second edition includes numerous updates, including greater coverage of CMOS PA design, RFIC design with on-chip components, and more worked examples with simulation results. By emphasizing working designs, this book practically transports readers into the authors' own RFIC lab so they can fully understand how these designs function. This title is suitable for radio frequency integrated circuit (RFIC) design engineers; radio systems architects; researchers and developers of RFIC technology; and, graduate level electrical engineering students.

Radio Frequency Integrated Circuit Design

Compositions, systems and methods that allow for the detection of the actual physical delivery of a pharmaceutical agent to a body are provided. Embodiments of the compositions include an identifier and an active agent. The invention finds use in a variety of different applications, including but not limited to, monitoring of therapeutic regimen compliance, tracking the history of pharmaceutical agents, etc.

Pharma-informatics system

A delay-locked loop (DLL) with wide-range operation and fixed latency of one clock cycle is proposed. This DLL uses a phase selection circuit and a start-controlled circuit to enlarge the operating frequency range and eliminate harmonic locking problems. Theoretically, the operating frequency range of the DLL can be from 1/(N/spl times/T/sub Dmax/) to 1/(3T/sub Dmin/), where T/sub Dmin/ and T/sub Dmax/ are the minimum and maximum delay of a delay cell, respectively, and N is the number of delay cells used in the delay line. Fabricated in a 0.35 /spl mu/m single-poly triple-metal CMOS process, the measurement results show that the proposed DLL can operate from 6 to 130 MHz, and the total delay time between input and output of this DLL is just one clock cycle. From the entire operating frequency range, the maximum rms jitter does not exceed 25 ps. The DLL occupies an active area of 880 /spl mu/m/spl times/515 /spl mu/m and consumes a maximum power of 132 mW at 130 MHz.

A wide-range delay-locked loop with a fixed latency of one clock cycle

A phase-locked loop (PLL) with a fast-locked discriminator-aided phase detector (DAPD) is presented. Compared with the conventional phase detector (PD), the proposed fast-locked PD reduces the PLL pull-in time and enhances the switching speed, while maintaining better noise bandwidth. The synthesizer has been implemented in a 0.35-/spl mu/m CMOS process, and the output phase noise is -99 dBc/Hz at 100-kHz offset. Under the supply voltage of 3.3 V, its power consumption is 120 mW.

Fast-switching frequency synthesizer with a discriminator-aided phase detector

A successive approximation register-controlled delay-locked loop (SARDLL) has been fabricated in a 025-/spl mu/m standard n-well DPTM CMOS process to realize a fast-lock clock-deskew buffer for long distance clock distribution This DLL adopts a binary search method to shorten lock time while maintaining tight synchronization between input and output clocks The measured lock time of the proposed SARDLL is within 30 clock cycles at 100-MWz clock input The power dissipation is 33 mW (not including off-chip driver's) at a 11-V supply voltage while the measured rms and peak-to-peak jitter are 113 ps and 95 /spl mu/s, respectively

/pdf/clock-deskew-buffer-using-a-sar-controlled-delay-locked-loop-2qatrkr312.pdf

Clock-deskew buffer using a SAR-controlled delay-locked loop

A fast pipeline technique using single-phase, edge-triggered, ratioed, high-speed logic flip-flops and D flip-flops is introduced and analyzed. The circuits achieve high speed by reducing the capacitive load and sharing the delay between the combination logic blocks and the storage elements. Also it is suitable for realizing high-speed synchronous counters. A divide-by-128/129 and 64/65 dual-modulus prescaler using the proposed flip-flops is measured in 0.8 /spl mu/m CMOS technology with the operating clock frequency reaching as high as 1.8 GHz.

New dynamic flip-flops for high-speed dual-modulus prescaler

A 1-Gb/s 0.18- mum CMOS serial-link transceiver using multilevel pulse-width and pulse-amplitude modulation (PWAM) signaling and a pre-emphasis technique is presented. Based on the PWAM technique, the transmit signaling is implemented to effectively push high data rates through bandwidth- limited channels. The clock is implicitly embedded in the 4-bit data stream, and the associated overhead needed in the clock-and-data recovery circuitry can be mitigated. In addition, the pin count can be reduced by transferring the data channels and the clock channel over a single transmitted channel. The recovered clock has an rms jitter of 5.9 ps at 250 MHz, and the retimed data have an rms jitter of 13.7 ps at 250 Mb/s. The occupied die area is 1.65 X 1.40 mm2. The transmitter and receiver power consumption is 86 and 45 mW, respectively.

/pdf/a-pwm-and-pam-signaling-hybrid-technology-for-serial-link-w6a61du18m.pdf

Ching-Yuan Yang

Papers

A wide-range delay-locked loop with a fixed latency of one clock cycle

Fast-switching frequency synthesizer with a discriminator-aided phase detector

Clock-deskew buffer using a SAR-controlled delay-locked loop

New dynamic flip-flops for high-speed dual-modulus prescaler

A PWM and PAM Signaling Hybrid Technology for Serial-Link Transceivers