Chithra

Bio: Chithra is an academic researcher from Indian Institute of Technology Madras. The author has contributed to research in topics: Phase frequency detector & Phase detector. The author has an hindex of 1, co-authored 4 publications receiving 3 citations.

A Flexible 18-Channel Multi-Hit Time-to-Digital Converter for Trigger-Based Data Acquisition Systems

Abstract: This paper presents the design of a low power, compact multi-channel single-shot time-to-digital converter (TDC) capable of handling multiple hits per channel. The system has 17 hit channels and 1 trigger channel and is designed to meet the requirements of the iron calorimeter detector in the India-based neutrino observatory. The TDC core consists of a delay chain stabilized by a delay-locked loop (DLL) and synchronous counters. The digital backend is programmable to allow for multiple configurations during the operation. The common core to all channels with concurrent accessibility, choice of core clock frequency optimizing the trade-offs between performance, power and area, and optimal backend logic result in a compact and low power design. It achieves a single-shot precision better than 65 ps. The $0.13\,\mathrm {\mu m}$ chip occupies an active area of 3.72mm2 and consumes 3.4mW per channel. This paper also reviews the theory on how timing precision is defined for a single-shot TDC and explains how the test plan can be devised based on the jitter in the system.

Static Phase Offset Reduction Technique for Delay Locked Loops

Abstract: A new static phase offset reduction technique suitable for low bandwidth delay locked loops is proposed. Chopping, which is a well-known technique for offset reduction, can be easily applied to the phase detector. Applying it to the charge pump is non-trivial and requires complex circuitry. The proposed technique reduces the offset due to both PFD and the charge pump, without actually chopping the latter. Analysis of the proposed method shows an offset reduction at least by a factor of 2. A conventional DLL, a DLL with a chopped PFD, and the proposed DLL were designed in a 130 nm CMOS process to verify the proposed technique. Monte Carlo simulations with random process and mismatch variations show that the offset improves from 19.9 ps in the conventional technique to 1.7 ps in the proposed technique.

Auto-Zeroing Static Phase Offset in DLLs Using a Digitally Programmable Sensing Circuit

Abstract: This brief presents a static phase offset (SPO) reduction technique through auto-zeroing in a delay-locked loop (DLL). We propose a self-calibrated, digitally programmable, sensing circuit that can measure both the polarity and the magnitude of the SPO. The SPO is suppressed by tuning a pair of digital-to-time converters (DTCs) at the input of the phase frequency detector (PFD). The proposed technique enables run-time background calibration and can suppress the SPO caused by artifacts from the PFD, charge pump, and loop filter capacitor. Monte Carlo simulation results show that the SPO in a conventional DLL implementation improves from 12.92 ps to 0.90 ps when the proposed auto-zeroing technique is employed.

A Technique for Measuring Picosecond Delays Using Phase Modulation

Abstract: This paper presents a delay measurement technique leveraging the high accuracy in the amplitude/frequency measurements of a spectrum analyzer. The two signals whose phase difference is to be measured are combined to generate a single output that can be fed to the spectrum analyzer. The delay information is embedded in the form of phase modulation in this output signal, resulting in a spur at one-fourth of the input signal frequency. The magnitude of this spur is used for estimating the input delay. Monte Carlo simulations of the proposed method for an input delay of 10 ps gives an estimated delay with a mean of 10.25 ps and a standard deviation of 1.17 ps.

Recent Advances and Trends in Voltage-Time Domain Hybrid ADCs

Abstract: The benefits of technology scaling have fueled interest in voltage-time domain hybrid ADCs. The hybrid ADCs employing combinations of successive approximation register (SAR), time-to-digital converter (TDC), and voltage-controlled oscillator (VCO) architectures have become attractive alternatives for analog intensive ADCs, owning to the merits of digital-centric nature, low-voltage tolerance, and scaling-friendly circuits. This tutorial brief aims to summarize on the advancement of voltage-time domain hybrid ADCs. The scope of this brief includes the basics and motivations behind the hybrid ADCs, followed by the survey covering the performance breakthroughs of hybrid ADC in terms of low power, high speed, and high resolution, and discuss the contributions and drawbacks of these techniques and architectures. The future trends are derived finally.

An FPGA based 33-channel, 72 ps LSB time-to-digital converter

Abstract: This paper describes a 33-channel time-to-digital converter (TDC) implemented in FPGA. This TDC is developed for the time-of-flight measurements using resistive plate chamber (RPC) detectors in India-based Neutrino Observatory (INO) experiment. The 33-channel TDC is implemented in Xilinx Spartan-6 FPGA using flash architecture by utilizing the carry-chains of the FPGA. The TDC features a novel bit latching scheme for fine interpolators to avoid overwriting of the delay line bits. The TDC also implements a low resource-consuming calibration method to achieve stable resolution under PVT variations in multi-channel TDC implementation. The TDC has the least significant bit (LSB) resolution of ∼ 72.4 ps across the channels with 20 μ s dynamic range. The differential non linearity (DNL) and integral non linearity (INL) over 20 μ s dynamic range are ± 0.56 LSB and [ − 0.86, 0.76] LSB respectively. The TDC consumes a power of 12.12 mW per channel. All 33-channels are characterized; the channel-to-channel variation in precision is ∼ 3 ps. The precision of the pulse width measurements is ∼ 39 ps. This paper discusses various aspects of the TDC implementation.

Recent Advances and Trends in Voltage-Time Domain Hybrid ADCs

Abstract: The benefits of technology scaling have fueled interest in voltage-time domain hybrid ADCs. The hybrid ADCs employing combinations of successive approximation register (SAR), time-to-digital converter (TDC), and voltage-controlled oscillator (VCO) architectures have become attractive alternatives for analog intensive ADCs, owning to the merits of digital-centric nature, low-voltage tolerance, and scaling-friendly circuits. This tutorial brief aims to summarize on the advancement of voltage-time domain hybrid ADCs. The scope of this brief includes the basics and motivations behind the hybrid ADCs, followed by the survey covering the performance breakthroughs of hybrid ADC in terms of low power, high speed, and high resolution, and discuss the contributions and drawbacks of these techniques and architectures. The future trends are derived finally.

MATRIX16: A 16-Channel Low-Power TDC ASIC with 8 ps Time Resolution

Abstract: This paper presents a highly configurable 16-channel TDC ASIC designed in a commercial 180 nm technology with the following features: time-of-flight and time-over-threshold measurements, 8.6 ps LSB, 7.7 ps jitter, 5.6 ps linearity error, up to 5 MHz of sustained input rate per channel, 9.1 mW of power consumption per channel, and an area of 4.57 mm2. The main contributions of this work are the novel design of the clock interpolation circuitry based on a resistive interpolation mesh circuit and the capability to operate at different supply voltages and operating frequencies, thus providing a compromise between TDC resolution and power consumption.

Performance and Integration Results of a High Resolution Time-to-Digital Converter Designed for INO ICAL Experiment

Abstract: INO ICAL Experiment emphasis on studying various properties of atmospheric neutrinos. A 50 kton Iron Calorimeter and Resistive plate Chamber (RPC) in stacked geometry will be used to track neutrinos. Position and directional information are to be used to identify particle energies. RPC detector signal of rise time less than 1ns is amplified-discriminated and given to Digital Front End (RPC-DAQ). To measure these fast pulses, we designed a low power, compact multi-channel Delay Chain based time-to-digital converter (TDC) in a 0.13μm CMOS process which will be integrated with the RPC-DAQ module. This TDC is capable of handling multiple hits per channel with a single-shot precision better than 65.34 ps. A 4-line or 11-line serial peripheral interface (SPI) is used for readout and configuration. This paper presents the performance and integration results of this TDC.