Chow Seng Guan

Bio: Chow Seng Guan is an academic researcher. The author has contributed to research in topics: Modeling and simulation & Integrated circuit packaging. The author has an hindex of 1, co-authored 1 publications receiving 22 citations.

Thermal characterization of vias using compact models

Abstract: Thermal vias and balls are key elements in plastic ball grid array (PBGA) package thermal design as they enhance the package performance. Simulation is a versatile design optimization tool for characterizing the thermal vias and balls. However, the finer geometric details of the vias require excessive memory and modeling and simulation time. Different modeling concepts are being tried in the industry to include finer geometries in the package. This paper shows a methodology of developing compact thermal via models and validating the same with detailed models. The accuracy of compact thermal via models with respect to the detailed models has been determined using PBGA 352 as the test vehicle. It is found that the accuracy is within 3%. The simulation models of PBGA 352 have been validated by measurements and found that the accuracy of model is within 10%. Two and four layer PBGA 352s with different via configurations have been characterized with compact thermal via models, and design guidelines for PBGA 352 packages have been obtained.

Thermal via placement in 3D ICs

Abstract: As thermal problems become more evident, new physical design paradigms and tools are needed to alleviate them. Incorporating thermal vias into integrated circuits (ICs) is a promising way of mitigating thermal issues by lowering the thermal resistance of the chip itself. However, thermal vias take up valuable routing space, and therefore, algorithms are needed to minimize their usage while placing them in areas where they would make the greatest impact. With the developing technology of three-dimensional integrated circuits (3D ICs), thermal problems are expected to be more prominent, and thermal vias can have a larger impact on them than in traditional 2D ICs. In this paper, thermal vias are assigned to specific areas of a 3D IC and used to adjust their effective thermal conductivities. The thermal via placement method makes iterative adjustments to these thermal conductivities in order to achieve a desired maximum temperature objective. Finite element analysis (FEA) is used in formulating the method and in calculating temperatures quickly during each iteration. As a result, the method efficiently achieves its thermal objective while minimizing the thermal via utilization.

Placement of thermal vias in 3-D ICs using various thermal objectives

Abstract: As thermal problems become more evident, new physical design paradigms and tools are needed to alleviate them. Incorporating thermal vias into integrated circuits (ICs) is a promising way of mitigating thermal issues by lowering the effective-thermal resistance of the chip. However, thermal vias take up valuable routing space, and therefore, algorithms are needed to minimize their usage while placing them in areas where they would make the greatest impact. With the developing technology of three-dimensional integrated circuits (3-D ICs), thermal problems are expected to be more prominent, and thermal vias can have a larger impact on them than in traditional two-dimensional integrated circuits (2-D ICs). In this paper, thermal vias are assigned to specific areas of a 3-D IC and used to adjust their effective-thermal conductivities. The method, which uses finite-element analysis (FEA) to calculate temperatures quickly during each iteration, makes iterative adjustments to these thermal conductivities in order to achieve a desired thermal objective and is general enough to handle a number of different thermal objectives such as achieving a desired maximum operating temperature. With this method, 49% fewer thermal vias are needed to obtain a 47% reduction in the maximum temperatures, and 57% fewer thermal vias are needed to obtain a 68% reduction in the maximum thermal gradients than would be needed using a uniform distribution of thermal vias to obtain these same thermal improvements. Similar results were seen for other thermal objectives, and the method efficiently achieves its thermal objective while minimizing the thermal-via utilization.

3D Floorplanning with Thermal Vias

Abstract: 3D circuits have the potential to improve performance over traditional 2D circuits by reducing wirelength and interconnect delay. One major problem with 3D circuits is that their higher device density due to reduced footprint area leads to greater temperatures. Thermal vias are a potential solution to this problem. This paper presents a thermal via insertion algorithm that can be used to plan thermal via locations during floorplanning. The thermal via insertion algorithm relies on a new thermal analyzer based on random walk techniques. Experimental results show that, in many cases, considering thermal vias during floorplanning stages can significantly reduce the temperature of a 3D circuit.

Three-dimensional packaging for multi-chip module with through-the-silicon via hole

Abstract: This paper presents an innovative package design for multi-chip modules. The developed package has a flip-chip-on-chip structure. Four memory chips (DRAM for demonstration) are assembled on a silicon chip carrier with eutectic Sn-Pb solder joints. The I/Os of memory chips are fanned-in on the silicon chip carrier to form an area array with larger solder balls. An optional through-the-silicon via hole is made at the center of the chip carrier for underfill dispensing, if required. The whole multi-chip module is mounted on the printed circuit board by the standard surface mount reflow process. After the board level assembly, all specimens are inspected by X-ray and divided into two groups. One group is encapsulated with underfill and the other group is not. For those packages with encapsulation, the underfill is dispensed through the aforementioned via hole to encapsulate the solder joints and memory chips. Subsequently, scanning acoustic microscopy is performed to inspect the quality of underfill. Afterwards, all specimens are subject to the accelerated temperature cycling (ATC) test. During the ATC test, the electrical resistance of those packages is monitored. The experimental results show that the packages without underfill encapsulation may fail in less than 100 thermal cycles while those with underfill can last for more than 1,000 cycles. From the dye ink analysis and the cross-section inspection, it is identified that the packages without underfill have failure in the silicon chip carrier, right under the pads of large solder balls. The ATC test of packages with underfill encapsulation is still ongoing (no observable failure recorded up to 1,200 cycles). With this innovative package design, low profile and high density multi-chip modules can be implemented. Due to the unique package structure and underfill encapsulation, it is believed that good board level reliability can be achieved.

Thermal management of a 3D chip stack using a liquid interface to a synthetic jet cooled spreader

Abstract: The present investigation focuses on the design of a unique liquid interface thermal management solution for a 3D chip stack that is embedded within a cavity, in a heat spreader cooled by an array of synthetic jet actuators. The heat sink module was previously reported by the authors, who achieved an overall heat transfer coefficient of ∼70 W/m2.K. The radial heat sink exploits enhanced, small-scale heat transfer that is affected by a central array of synthetic jet actuators. This approach is very effective due to the short radial thermal path of the cooling air along the fins which couples rapid, time-periodic entrainment and ejection of cool and heated air, respectively to increase the local heat transfer coefficient on the air-side. The key focus of this paper is the numerical simulation of the dielectric liquid interface used to efficiently transmit the heat from the high power 3D stacked electronics to the heat sink base. The coupled natural convection in the fluid and conduction in solid spreaders sandwiched between the tiers of the stack form a novel efficient, passive and scalable thermal management solution.