Author
Christian Landrault
Bio: Christian Landrault is an academic researcher from University of Montpellier. The author has contributed to research in topics: Automatic test pattern generation & Fault coverage. The author has an hindex of 23, co-authored 105 publications receiving 1959 citations.
Papers published on a yearly basis
Papers
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29 Mar 2001TL;DR: A new low power test-per-clock BIST test pattern generator that provides test vectors which can reduce the switching activity during test operation and numerous advantages can be found in applying such a technique during BIST.
Abstract: In this paper, we present a new low power test-per-clock BIST test pattern generator that provides test vectors which can reduce the switching activity during test operation. The proposed low power/energy BIST technique is based on a modified clock scheme for the TPG and the clock tree feeding the TPG. Numerous advantages can be found in applying such a technique during BIST.
154 citations
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19 Nov 2001TL;DR: A novel approach for minimizing power consumption during scan testing of integrated circuits or embedded cores is presented, based on a gated clock scheme for the scan path and the clock tree feeding thescan path.
Abstract: Test power is now a big concern in large system-on-chip designs. In this paper, we present a novel approach for minimizing power consumption during scan testing of integrated circuits or embedded cores. The proposed low power technique is based on a gated clock scheme for the scan path and the clock tree feeding the scan path. The idea is to reduce the clock rate on scan cells during shift operations without increasing the test time. Numerous advantages can be found in applying such a technique.
153 citations
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31 May 1998TL;DR: The proposed approach is based on a re-ordering of the vectors in the test sequence to minimize the switching activity of the circuit during test application and guarantees a decrease in power consumption and heat dissipation.
Abstract: This paper considers the problem of testing VLSI integrated circuits without exceeding their power ratings during test. The proposed approach is based on a re-ordering of the vectors in the test sequence to minimize the switching activity of the circuit during test application. Our technique uses the Hamming distance between test vectors and guarantees a decrease in power consumption and heat dissipation without modifying the initial fault coverage. Results of experiments are presented at the end of this paper and shows a reduction of the circuit activity in the range from 8.2 to 54.1% during test application.
120 citations
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07 Oct 2002TL;DR: A novel approach for scan cell ordering which significantly reduces the power consumed during scan testing is presented, based on the use of a two-step heuristic procedure that can be exploited by any chip layout program during scan flip-flops placement and routing.
Abstract: Power consumption during scan testing is becoming a primary concern. In this paper, we present a novel approach for scan cell ordering which significantly reduces the power consumed during scan testing. The proposed approach is based on the use of a two-step heuristic procedure that can be exploited by any chip layout program during scan flip-flops placement and routing. The proposed approach works for any conventional scan design and offers numerous advantages compared with existing low power scan techniques. Reductions of average and peak power consumption during scan testing are up to 58% and 24% respectively for experimented ISCAS benchmark circuits.
110 citations
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30 Sep 2003
TL;DR: A new technique is presented that allows to design power-optimized scan chains under a given routing constraint based on clustering and reordering of scan cells in the design and allows to reduce average power consumption during scan testing.
Abstract: Scan-based architectures, though widely used in modern designs, are expensive in power consumption. In this paper, we present a new technique that allows to design power-optimized scan chains under a given routing constraint. The proposed technique is a three-phase process based on clustering and reordering of scan cells in the design. It allows to reduce average power consumption during scan testing. Owing to this technique, short scan connections in scan chains are guaranteed and congestion problems in the design are avoided.
90 citations
Cited by
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TL;DR: This survey summarizes, classifies, and compares various existing maintenance policies for both single-unit and multi-unit systems, with emphasis on single- unit systems.
1,507 citations
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20 Sep 2004
1,387 citations
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01 Jul 2006
TL;DR: This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time- to-volume.
522 citations
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TL;DR: The author reviews low-power testing techniques for VLSI circuits with a discussion of power consumption that gives reasons for and consequences of increased power during test.
Abstract: The author reviews low-power testing techniques for VLSI circuits. He prefaces this with a discussion of power consumption that gives reasons for and consequences of increased power during test. He ends with a discussion of the opportunity to use such techniques in varying situations.
430 citations
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21 Jul 2006
TL;DR: A comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time to market and time-to-volume as mentioned in this paper.
Abstract: This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume.
· Most up-to-date coverage of design for testability.
· Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books.
· Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures.
· Lecture slides and exercise solutions for all chapters are now available.
· Instructors are also eligible for downloading PPT slide files and MSWORD solutions files from the manual website.
Table of Contents
Chapter 1 - Introduction
Chapter 2 - Design for Testability
Chapter 3 - Logic and Fault Simulation
Chapter 4 - Test Generation
Chapter 5 - Logic Built-In Self-Test
Chapter 6 - Test Compression
Chapter 7 - Logic Diagnosis
Chapter 8 - Memory Testing and Built-In Self-Test
Chapter 9 - Memory Diagnosis and Built-In Self-Repair
Chapter 10 - Boundary Scan and Core-Based Testing
Chapter 11 - Analog and Mixed-Signal Testing
Chapter 12 - Test Technology Trends in the Nanometer Age
340 citations